Abstract: The soft decisions associated with the quadrature digital signals received are calculated on the basis of at least one parametric law slaved to the minimum value of the rate of erroneous bits. The value is determined at the output of a Viterbi decoder in a microcontroller by varying the parameter of the law. The approach may be applied to applications including terrestrial digital broadcasting according to the DVB-T standard using OFDM modulation.

Abstract: An operational amplifier is provided that includes an inverting input channel, a non-inverting input channel, and an output stage. Each of the input channels controls at least one input transistor, and the output stage supplies an output voltage as a function of a potential difference at the input channels. Additionally, the operational amplifier includes at least one signal correction element in association with at least one of the input channels. The signal correction element is selectively put into circuit to selectively add an offset voltage correction signal to a signal that is supplied to the output stage in order to balance the characteristics of the two input channels. Also provided is a circuit for correcting the offset voltage of an operational amplifier.

Abstract: A method of packaging a chip made in a semiconductor wafer. The method includes providing, on a first surface of the wafer, a conductive area extending beyond the periphery of the chip; adding a first thick plate including an electrically isolating material on the first surface; etching the conductive layer from a second surface of the wafer and depositing a conductive track extending from a contact of the second chip surface to the exposed surface of the conductive area; covering the second surface with a second thick plate forming a rigid cap; and etching the first plate above the conductive layer to deposit thereon a conductive material extending, in the form of a track, to the exposed surface of the first plate.

Abstract: An amplifier includes an input stage with one or more input terminals for receiving a signal to be amplified, and an output terminal. An inverting gain stage includes an input terminal connected to the output terminal of the input stage, an output terminal for delivering an amplified signal, and a variable feedback resistor connected between the output terminal and input terminal thereof. The input stage is a transconductor stage biased by a current source. A transconductance thereof is set by a resistor of the current source so that the amplifier has a gain proportional to the product of the variable feedback resistor multiplied by the transconductance.

Abstract: An electronic device, such as an opto-electronic device and an integrated semiconductor memory device, includes at least one integrated memory point structure including a quantum well semiconductor area buried in the substrate of the structure and disposed under the insulated gate of a transistor. A biasing voltage source is adapted to bias the structure to enable charging or discharging of charges in the quantum well or outside the quantum well.

Abstract: In a method for the display of text on a screen of a television receiver, the digital data representing a received text are decoded to give, first, a list of characters to be displayed including at least one character and a color palette including at least one color, and second, a matrix of pixels associated with the list of characters to be displayed. Each element of the matrix of pixels defines the color of a corresponding point of the screen. To obtain a visual effect on at least one point of the screen, at least one color of the color palette is modified. The display method may be implemented in a television receiver.

Abstract: A circuit is provided for reducing losses of the start of a new message caused by the microcontroller of a slave apparatus being unavailable. The circuit generates an interruption signal when the slave apparatus has received and acknowledged a start of a new message but the microcontroller is unavailable because it is processing a preceding message or an application of the slave apparatus.

Abstract: A process for fabricating a metal-metal capacitor within an integrated circuit comprises the steps of: producing a first metal electrode, a second metal electrode, and a dielectric layer on top of a lower insulating layer; and depositing an upper insulating layer on top of the two metal electrodes and the dielectric layer. The integrated circuit comprises the insulating layer, a first metal layer which is on top of the lower insulating layer, and the upper insulating layer which is on top of the first metal layer. The capacitor comprises the first metal electrode, the second metal electrode, and the dielectric layer wherein each of the two metal electrodes is in contact with one side of the dielectric layer. The electrodes and the dielectric layer lie between the lower insulating layer, which supports a level of metallization (M1), and the upper insulating layer which covers this level of metallization.

Abstract: The operation Y0=(X*J0) mod 2Bt is implemented directly within a coprocessor to eliminate the need for, a register of Bt=m*k bits within the coprocessor. This eliminated register enables the storage of a data element during the computation of Y0. The operation S=A*B mod 2m*k is implemented with a circuit including at least three registers and a multiplication circuit. One of the registers simultaneously stores S and an intermediate result. To improve the method, a second multiplication circuit and registers of variable sizes are used.

Abstract: An integrated circuit includes an array of memory cells that are selected by rows and read by columns. The columns are first precharged by an internal signal to then read the memory cells. The read is responsive to an edge of a clock signal and the read is of an unknown delay. A multiplexer output provides the internal signal. The multiplexer includes a plurality of inputs electrically connected to delay lines of different delay sizes that receive the edge of the clock signal. A multiplexer control circuit selects a delay line to provide the internal signal as soon as possible after the unknown delay.

Abstract: A master-slave D type flip-flop circuit includes a power consumption masking circuit including a reference stage in parallel with a master and a slave stage of the flip-flop circuit. This structure advantageously provides a switching of the flip-flop circuit on each of the leading and trailing edges of the clock signal for the sequencing of the flip-flop circuit.

Abstract: An integrated circuit includes a first and second memory, with the first memory being configurable between a first data format and a second data format. An external address bus is connected to the second memory, and an internal bus is connected to the first memory. A rerouting circuit is connected between the external address bus and the internal bus. The rerouting circuit forms one of two connections between the external address bus and the internal bus dependent upon the configuration of the first memory.

Abstract: A BPSK encoder is provided with a first circuit which processes a carrier signal and a binary signal to be encoded, and produces an output binary signal having synchronous phase shifts representing a change in the value of the signal to be encoded. Also, the first circuit is provided with a sampling signal from a second circuit. The second circuit includes a delay circuit to deliver a shifted carrier signal that is smaller than the half-period of the carrier signal, and a logic gate for the logic combination of the carrier signal and the shifted carrier signal. The logic gate also delivers a binary sampling signal having at least two leading or trailing edges at each period of the carrier signal.

Abstract: An initial single-crystal substrate 1 having, locally and on the surface, at least one discontinuity in the single-crystal lattice is formed. The initial substrate is recessed at the discontinuity. The single-crystal lattice is amorphized around the periphery ofthe recess. A layer ofamorphous material having the same chemical composition as that ofthe initial substrate is deposited on the structure obtained. The structure obtained is thermally annealed in order to recrystallize the amorphous material so as to be continuous with the single-crystal lattice ofthe initial substrate.

Abstract: A method for communicating between a transmitting unit and a receiving unit. A messages formed by elementary messages is transmitted from the transmitting unit to the receiving unit, and at least one reception bit is transmitted from the receiving unit to the transmitting unit. The reception bit (or bits) allows the transmitting unit to determine the elementary message that is to be transmitted next. In a preferred method, at least two reception bits are transmitted from the receiving unit and the values of the reception bits indicate the elementary message that is to be transmitted next by the transmitting unit. The present invention also provides a receiving device for receiving messages from a transmitting device. The receiving device includes an interface for receiving a transmitted message from the transmitting device, means for analyzing a received elementary message to determine if it was properly received, and a transmitter for transmitting at least one reception bit to the transmitting device.

Abstract: A voltage regulating device includes a comparison circuit for comparing a voltage proportional to an output voltage to a fixed reference voltage. The fixed reference voltage is received on a first input and the voltage proportional to an output voltage is received on a second input. The voltage regulating device further includes a variable resistance-forming circuit controlled by the output of the comparison circuit and disposed so that the output voltage remains substantially constant. The voltage regulating device may be supplied with a variable input voltage. The voltage regulating device further includes a second comparison circuit so that the output voltage remains substantially constant if the input voltage is greater than a threshold, and substantially equal to the input voltage if the input voltage is less than the threshold.

Abstract: A method for storing pages of a teletext service, with at least one page being received by a storage circuit of a television receiver, is provided. The storage circuit includes a data memory for storing the at least one received page. The method includes extracting a reference number from the at least one received page, checking whether the at least one received page is a requested page, and evaluating contents of the data memory to decide whether the at least one received page is to be stored as a function of free space in the data memory and an importance of the at least one received page. The method also includes storing the at least one received page if it is decided that the at least one received page is to be stored.

Abstract: An OTP memory cell in CMOS technology, including a capacitor associated in series with an unbalanced programming transistor, the drain of which is made of a region deeper and less doped than the source.

Abstract: A method of cutting a wafer of a semiconductor material, including breaking the wafer along cutting paths using a knife hitting a sheet supporting the wafer in a frame. The method includes using knives of different lengths according to the wafer region in which the cutting path is located using a tool block including apparatus for receiving at least two knives of different lengths and for rotating step-by-step around an axis to change the knife that is active in the wafer cutting.

Abstract: A ROM including an array, each cell of which is accessible by means of a column address and of a row address, includes a parity memory for storing the expected parity of each row and of each column, an electrically programmable one-time programmable address memory, a testing circuit for, during a test phase, calculating the parity of each row and of each column, comparing the calculated and expected parities for each row and each column, and in case they are not equal, marking the row or column in the address memory, and a correction circuit for, in normal mode, inverting the value read from the array cell, having its row and column marked in the address memory.