Abstract: A column register of an integrated circuit memory, notably in EEPROM technology, is utilized in a method of writing a data word of 2p bits in the memory, where p is a non-zero whole number. The method includes the following steps: 1) erasing all the cells of the word; 2) loading 2q data in 2q high-voltage latches (HV1, HV3, HV5, HV7), and loading 2p-2q other data in the 2p-2q low-voltage latches (LV0, LV2, LV4, LV6); and 3) programming 2q cells of the memory (M0, M2, M4, M6) as a function of the data memorized in the 2q high-voltage latches; as well as repeating 2p-q−1 times the following steps: 4) loading, in the 2q high-voltage latches, of 2q other data that were loaded in the 2q low-voltage latches at step 2); and 5) programming 2q other cells of the memory (M1, M3, M5, M7) as a function of the data memorized in the 2q high-voltage latches.

Abstract: A non-volatile memory cell includes a MOS transistor having a ring arrangement and comprising a floating gate, a center electrode at a center of the ring arrangement and surrounding the floating gate, and at least one peripheral electrode along a periphery of the ring arrangement.

Abstract: At least a first base signal and a second base signal are mutually in quadrature and both are capable of mutually exhibiting a quadrature error. These signals are used to formulate two pairs of delayed signals that includes a first delayed signal that is delayed with respect to the first base signal, a second signal delayed in phase opposition with respect to the first delayed signal, a third signal delayed with respect to the second base signal, and a fourth delayed signal in phase opposition with respect to the third delayed signal. The value of each of the delays is continuously adjusted using two differential signals arising from a direct or an indirect cross-mixing of the two pairs of delayed signals to obtain the four delayed signals virtually in quadrature.

Abstract: A monolithic bidirectional switch formed in a semiconductor substrate of a first conductivity type having a front surface and a rear surface, including a first main vertical thyristor, the rear surface layer of which is of the second conductivity type, a second main vertical thyristor, the rear surface layer of which is of the first conductivity type. A structure for triggering each of the first and second main thyristors is arranged to face regions mutually distant from the two main thyristors, the neighboring portions of which correspond to a region for which, for the first main thyristor, a short-circuit area between cathode and cathode gate is formed.

Abstract: A method and device reduces consumption of a microcontroller, allowing the microcontroller to enter into an “active halt” mode in which the central processing unit, the internal peripheral circuits, and a clock tree are deactivated. The main oscillator is operative and delivers an oscillating signal. An internal interruption returns the microcontroller back into the run mode and is generated after a time delay obtained by an internal circuit activated by the oscillating signal.

Abstract: Electronic circuit comprising a first and a second current mirrors, an upstream active element arranged between an input of the first current mirror and an input of the second current mirror, each current mirror being provided with an output. The circuit comprises a first current source arranged in parallel with the input of the first current mirror and a second current source arranged in parallel with the input of the second current mirror, so that the current delivered to the active element is equal to the output current of each current mirror and that the input current of each current mirror is less than the current delivered to the active element by the input of each current mirror and by the associated current source.

Abstract: A process and an integrated circuit are intended for obtaining an adjustable electrical resistance, in which a first voltage is applied to an integrated MOS transistor on its source, its gate and its substrate, and a second voltage is applied on its drain, the first and second voltages being able to initiate a breakdown of the MOS transistor by: avalanche of the drain/substrate junction; biasing of the parasitic bipolar transistor of the MOS transistor; irreversible breakdown of the drain/substrate junction; and shorting between the drain and the source.

Abstract: The present invention relates to a method for determining a characteristic of a periodic digital signal, including the steps of: defining a measurement period such that the ratio between the measurement period and the period of the digital signal is a ratio of integers; selecting a set of measurement periods in which the digital signal has substantially the same phase; defining a measurement time having a same position in each measurement period of the set; storing the value of the digital signal at each measurement time; shifting the measurement time by a predetermined pitch lower than one measurement period; repeating the two preceding steps until the measurement time of each measurement period has scanned a predetermined portion of the measurement period; and analyzing the succession of the noted values.

Abstract: A configurable electronic circuit having configuration nodes is provided. Each of the configuration nodes is coupled to corresponding first circuitry that is non-modifiable during configuration and second circuitry that is modifiable during the configuration. The non-modifiable first circuitry selectively imposes one of at least a first potential and a second potential on the configuration node prior to configuration, and the modifiable second circuitry allows modification of the potential imposed on the configuration node by the non-modifiable first circuitry. In a preferred embodiment, the modifiable second circuitry includes at least one fuse that is in an intact state before configuration and that can be changed to a destroyed state after configuration. This enables a reduction in the number of fuses that have to be destroyed during the configuration of the circuit. Also provided is an information processing system that includes at least one configurable electronic circuit having configuration nodes.

Abstract: The present invention relates to a method of manufacturing the base and emitter regions of a bipolar transistor, including the steps of depositing a first heavily-doped P-type polysilicon layer; eliminating the first polysilicon layer in its central portion; growing a thermal oxide layer; performing a P-type implantation at a first dose; forming silicon nitride spacers at the internal periphery of the first layer; performing a second P-type implantation at a second dose; eliminating the central oxide layer; depositing a second N-type polysilicon layer; and performing a fast thermal anneal; the second dose being selected to optimize the characteristics of the base-emitter junction and the first dose being smaller than the second dose.

Abstract: A power-on-reset circuit for delivering a power-on-reset pulse when a supply voltage ramps up from zero to a predetermined voltage includes a pull-down circuit portion for connecting an output node of the power-on-reset circuit to ground when the supply voltage reaches a predetermined upper threshold voltage and a pull-up circuit portion for connecting the output node to the supply voltage when the supply voltage reaches a predetermined upper threshold voltage. The pull-up circuit portion includes a transistor whose gate is polarized by a reference voltage taken at the terminals of a precision resistance traversed by a current delivered by a current generator, where the current is preferably a band-gap current proportional to the temperature of the circuit. The power-on-reset circuit is particularly suitable for microprocessors.

Abstract: A circuit for checking the parity of the contents of a register is provided. The register has a test mode in which a scan input of each flip-flop in the register is connected to a scan output of a preceding flip-flop to form a scan path. The parity checking circuit includes an XOR gate for at least each flip-flop from the second flip-flop to the last flip-flop of the register. Each XOR gate has one input connected to the normal output of the associated flip-flop, another input connected to the scan input for the flip-flop, and an output connected to the scan output of the flip-flop when not in the test mode. The result of the parity checking operation is generated at the output of the XOR gate associated with the last flip-flop of the register. In preferred embodiments, for each flip-flop of the register, the normal output of the flip-flop is supplied to the scan output in the test mode, and the output of the associated XOR gate is supplied to the scan output when not in the test mode.

Abstract: A method for manufacturing a smart card in which a through-passage is produced in a central sheet. At least one face of the central sheet is provided with at least one metal coil having connection parts, and an electronic chip having electrical connection pads is inserted into the passage. At least some of the electrical connection pads of the chip are soldered to the connection parts of the coil, and the faces of the central sheet are provided with external covering sheets to form a stack of sheets. In a preferred method, the stack of sheets is hot pressed or laminated such that the material of the sheets is flowed and fills the space around the chip. A smart card is also provided. The smart card includes at least one metal coil having at least two connection parts, an electronic chip connected to the connection parts of the coil, a central sheet having a through-passage, and external covering sheets that grip the central sheet. The electronic chip is placed in the passage in the central sheet.

Abstract: A micro-pipeline type asynchronous circuit and a method for detecting and correcting soft error. The asynchronous circuit records in a first recording unit a signal output by a calculation unit and then records in a second recording unit the same signal delayed by at least the duration of the pulse of a soft error. The recorded signals then are compared in a comparer circuit. If they are identical, no soft error has been detected and the output signal is recorded after another delay that is longer than the pulse duration of the soft error, and a request signal is transmitted to a control unit of a next logic stage with a delay twice as long as the pulse duration of a soft error.

Abstract: A high-voltage bidirectional switch, including a high-voltage bidirectional switching element, and circuitry for making the switching element bistable and controllable by, at most, two low-voltage pulse signals.

Abstract: An integrated circuit memory including an array of memory cells divided into several sections, and several rows of column decoding amplifiers, the respective outputs of which are interconnected, by column, by means of a decoded bit line, each decoded bit line including two perpendicular sections, one of which is in the row direction to directly connect each decoded bit line to an input of an input-output stage of the memory arranged at one end of the rows.

Abstract: A zero crossing control circuit of a bidirectional switch including two transistors of complementary types connected in parallel between the gate of the bidirectional switch and the main reference terminal of the bidirectional switch, the gate of the bidirectional switch being connected to a control source via a first resistor, and each of the control terminals of the transistors being connected to the second main terminal of the bidirectional switch via a second resistor of high value, a zener diode being interposed between the second resistor and each of the control terminals according to a biasing adapted to turning on each of the transistors when the zener threshold is exceeded.

Abstract: A method of forming, on a single-crystal semiconductor substrate of a first material, quantum dots of a second material, including growing by vapor phase epitaxy the second material on the first material in optimal conditions adapted to ensuring a growth at a maximum controllable rate. In an initial step, a puff of a gas containing the second material is sent on the substrate, in conditions corresponding to a deposition rate much faster than the maximum controllable rate.

Abstract: A digital signal output circuit is provided. The digital signal output circuit includes capacitor forming means connected as an integrator, charging means, discharging means, means for selectively coupling, and a digital signal output. The charging means selectively charges the capacitor forming means with a constant charging current, and the discharging means selectively discharges the capacitor forming means with a constant discharging current. The means for selectively coupling selectively couples the capacitor forming means to the charging means and to the discharging means as a function of data to be transmitted by the digital signal. Additionally, the digital signal output is coupled to the capacitor forming means so as to establish a rising edge of the digital signal when the capacitor forming means is coupled to the charging means and a falling edge of the digital signal when the capacitor forming means is coupled to the discharging means.

Abstract: A preamplifier including an input stage adapted to receiving an analog signal via a connection capacitor, and a differential output stage adapted to providing the signal referenced with respect to a predetermined level, and circuitry for enabling the input stage to accept a signal referenced to the differential stage ground, the signal provided by the output stage being referenced to this ground.