Abstract: The computation time of modular operations on large-format data is improved by using a computation circuit integrated as a modular arithmetic coprocessor. The computation circuit carries out an S=A*B+C type operation, with S and C encoded on 2*Bt bits, and A and B encoded on Bt bits. To carry out this operation, a storage flip-flop circuit enables the storage of a possible overflow carry value at the end of an elementary computation, and reinserts this carry value during the following computation.

Abstract: The vertical bipolar transistor includes an SiGe heterojunction base formed by a stack of layers of silicon and silicon-germanium resting on an initial layer of silicon nitride extending over a side insulation region surrounding the upper part of the intrinsic collector. The stack of layers also extends on the surface of the intrinsic collector which lies inside a window formed in the initial layer of silicon nitride.

Abstract: A tuner includes an analog block, a digital block, and an analog/digital conversion stage connected therebetween. The analog block includes a first attenuator/controlled-gain amplifier stage connected upstream to a frequency transposition stage. The overall mean power of the entire signal received by the tuner is calculated during a phase of initialization. This overall calculated power is compared in the digital block with a first predetermined reference value corresponding to a maximum power desired at a predetermined location of the analog block. The gain of the first attenuator/amplifier stage is adjusted to minimize the deviation between the overall calculated power and the reference value. In a phase of normal operation, one of the channels of the signal received is selected, with the gain of the first attenuator/ amplifier stage being fixed.

Abstract: A method is for the preparation and execution of a self-test procedure to validate the behavior of a processor model to be tested. The processor model may be a processor or an associated simulator. The method provides self-test procedures that are immediately executable by all the models of a processor and that give OK/ERROR type results that are easy to interpret.

Abstract: A comparator of a first digital value of n bits having CMOS voltage levels with a second digital value of n bits having ECL, or CML voltage levels, including a decoder in CMOS technology provided to provide 2n CMOS signals, each of which corresponds to a different product of n bits, each of the n bits being a respective bit of the first digital value or its complement; 2n AND gates in ECL or CML technology respectively associated with the 2n CMOS signals, connected to implement an OR function of 2n ECL or CML signals, each of which corresponds to a different product of n bits taken from among the bits of the second value or their complements, according to the same choice as for the product of n bits of the respective CMOS signal; and means for deactivating the AND gates associated with the CMOS signals to 0.

Abstract: A voltage regulation device is for a reference cell of a dynamic random access memory arranged in lines and columns and including a plurality of memory cells. The device includes at least one capacitor of a predetermined capacitance which can be discharged during memory access.

Abstract: An electronic circuit with digital output including an auto-stable assembly of latches (1), a control assembly (2), a blowable assembly (3), a logic gate (4) including a first input connected to a common point (14) between the auto-stable assembly (1) and the blowable assembly (3), and a second input connected to the control input (20) of the electronic circuit. A breaker (5) is controlled by the output of the logic gate (4) and arranged between the auto-stable assembly (1) and ground, and an associated process.

Abstract: A method for making a MOS transistor includes forming a first gate within a silicon-on-insulator substrate, forming a semiconductor channel region transversely surmounting the first gate, and forming semiconductor drain and source regions on each side of the channel region. The semiconductor channel region and drain and source regions may be produced by epitaxy on an upper surface of the first gate. The channel region may be isolated from the upper surface of the first gate by forming a tunnel under the channel region and at least partially filling the tunnel with a first dielectric. The second gate is formed on the channel region and transverse to the channel region. The second gate may be separated from an upper surface of the channel region by a second dielectric.

Abstract: A self-aligned double-polysilicon type bi-polar transistor with a heterojunction base comprises a semiconducting heterojunction region lying over an active region of a semiconductor substrate and over an isolating region delimiting the active region, and incorporating the intrinsic base region of the transistor. An emitter region situated above the active region and coming into contact with the upper surface of the semiconducting heterojunction region. A polysilicon layer forming the extrinsic base region of the transistor, situated on each side of the emitter region and separated from the semiconducting heterojunction region by a separation layer comprising an electrically conducting connection part situated just outside the emitter region. This connection part ensures an electrical contact between the extrinsic base and the intrinsic base.

Abstract: A non-volatile memory includes a floating gate extending in a substrate between source and drain regions. A channel region may be confined by two insulating layers. The invention is particularly applicable to EPROM, EEPROM, Flash and single-electron memories using CMOS technology.

Abstract: A voltage regulator includes a regulation MOS transistor with low serial resistance having a first terminal connected to a voltage source and a second terminal connected to the output of the voltage regulator and an amplifier having an output driving a gate of the transistor. The gate is driven based upon a difference between a reference voltage and a feedback voltage. The regulator may also include an anti-overshoot switch with a first terminal connected to the gate of the regulation MOS transistor and a second terminal is taken to a potential for turning the regulation MOS transistor off. A switch controller closes the switch when the output voltage of the regulator is higher than a first threshold. The first threshold may be higher than the nominal value of the output voltage.

Abstract: The process includes successively forming, over a base region of a semiconductor substrate, a poly-Ge or poly-SiGe layer, an etch-stop layer over a selected zone of the Ge or SiGe layer, a layer of poly-Si of the same conductivity type as the base region, then an outer layer of dielectric material. Etching the layers includes stopping at the stop layer to form an emitter window preform, removing the stop film and selectively removing the Ge or SiGe layer in the emitter window preform to form an emitter window and to form an emitter made of poly-Si of conductivity type the opposite of the base region in the window.

Abstract: A system for the detection of a load modulation signal by inductive coupling includes an antenna circuit having a coil, a circuit for applying an excitation signal having a predetermined frequency to the antenna circuit, and a current sensor for detecting a current signal in the coil. A phase comparator has a first input receiving the excitation signal, and has a second input receiving the current signal detected by the current sensor. The system also includes a circuit for extracting the load modulation signal from a phase signal provided by the phase comparator. The antenna circuit does not form a resonant circuit equal to or near the predetermined frequency of the excitation signal.

Abstract: A method is provided for identifying electronic cards. According to the method, an interrogation message is sent to the electronic cards, and at least two different types of markers are sent to the electronic cards. The markers of the first type determine the time slots in the sequence, and the markers of the second type cause the electronic cards to change to predetermined states. In a preferred method, the identification method is interrupted when a marker of the second type is sent. Also provided is a method of identifying electronic cards by receiving an interrogation message from an interrogation unit, and at least two different types of markers are received from the interrogation unit. The markers of the first type determine the time slots in the sequence, and the markers of the second type cause the electronic cards to change to predetermined states. Additionally, communication systems of the type in which an interrogation unit identifies electronic cards are provided.

Abstract: A monolithic power switch with a controlled di/dt including the parallel assembly of a MOS or IGBT type component with a thyristor type component, including means for inhibiting the thyristor type component during the closing phase of the switch, which is ensured by the IGBT type component. The IGBT type component has a vertical multicell structure and the component of thyristor type has a vertical monocell structure.

Abstract: A method is provided for correcting flicker and flutter of an OSD on a video image. According to the method, values of pixels of the OSD are stored, pixels of lines of the OSD that are to be displayed without processing are substituted for pixels of the video image, and pixels of lines of the OSD that are to be displayed after processing are subjected to a mathematical filter. In the subjecting step, the value of another pixel of the video image is assigned to each pixel of the video image that is required by the mathematical filter but presently unavailable, with the other pixel belonging to the same column as the required pixel. In a preferred embodiment, the required pixel is a pixel of the video image that is not covered by the OSD, and the other pixel belongs to the closest line of the video image that is covered by the OSD. This makes it possible to simplify the use of mathematical filters associated with a unique equation for all of the lines of the overlaid OSD.

Abstract: For each input block of N data bits received as an input to a stage for computing a Fourier transform, only three quarters of the data bits of the input block are stored in a main storage. A Fourier transform computation is performed on the basis of the stored data and of the other data of the block. Only half of the data bits received are stored in an auxiliary storage. All the data bits of the input block are reconstructed from the contents of the main and auxiliary storage to obtain a reconstructed data block, which is temporally delayed with respect to the input block.

Abstract: In a reading device for a memory, a circuit for the asymmetrical precharging of the differential amplifier is provided so that an output of the reading device switches over to a determined state. In the following evaluation phase, if the memory cell is programmed, the output remains unchanged. If the memory cell is blank or erased, the output of the reading device switches over to another state. A detection circuit detects a sufficient difference between the inputs of the differential amplifier for stopping the asymmetrical precharging and for making the reading device go automatically to the evaluation phase.

Abstract: An integrated circuit includes a microprocessor driven by an internal clock signal and at least one internal peripheral circuit activated selectively by the microprocessor to perform an operation, wherein said circuit includes a circuit for matching the period of the internal clock signal to the operating time of the activated internal peripheral circuit. The integrated circuit can be used as part of any microcontroller.

Abstract: A method for the identification of electronic cards within an investigation zone includes an identification number uniquely assigned to each electronic card. The method reconstructs the identification numbers according to a tree-like iterative algorithm. The algorithm includes the steps of sending an interrogation message intended for certain electronic cards present, and steps for sending a response message by the electronic cards. The response message includes a variable number whose value depends on the identification number of the electronic card. The interpretation of the existence and of the position at which a collision occurs between the bits of the variable numbers received enables the gradual reconstruction, possibly by blocks of bits, of the as yet unidentified bits of an identification number of an electronic card present.