Abstract: An amplifier circuit including at least one first input amplifier; at least one second amplifier cascode-assembled with the first amplifier; and at least one reactive impedance circuit, mounted in series with the second amplifier, the reactive impedance circuit being formed by two impedances respectively exhibiting a maximum value for a first and a second frequency, to form a double-band amplifier circuit.

Abstract: A control device is provided for controlling a selector switch of a high voltage input having at least one cascode stage with MOS transistors. The control device includes a reference voltage generation circuit and a control circuit. The reference voltage generation circuit generates reference voltages from the high voltage input and provides one or more output voltages for the biasing of the MOS transistors of the cascode stage. The control circuit controls the reference generation circuit on the basis of a binary control signal, so as to either set the bias voltages at the level of the logic supply voltages to enable the switching of the selector switch even at low values of the high voltage input, or to enable the bias voltages to be set by the reference generation circuit.

Abstract: A test structure includes a single current-measuring means for measuring current between a supply terminal and ground, and first and second branches for measuring capacitance between first and second metal lines. The first branch includes a first switch coupled between the current-measuring means and the first line, and a second switch coupled between the first line and ground. Similarly, the second branch includes a third switch coupled between the current-measuring means and the second line, and a fourth switch coupled between the second line and ground. A method for testing a circuit is also provided.

Abstract: A device for the regeneration of a clock signal from an external serial bus includes a ring oscillator and counter. The ring oscillator provides n phases of a clock signal. Of these n phases, one phase is used as a reference and is applied to the counter. It is thus possible to count the number of entire reference clock signal periods between a first pulse and a second pulse received from the bus. In reading the state of the phases in the oscillator upon reception of the second pulse, a determination is made for a current phase corresponding to the phase delay between the reference clock signal and the second pulse of the bus. By using a regeneration device that also includes a ring oscillator and a counter, it is possible to regenerate the clock signal of the bus with high precision.

Abstract: A voltage regulator includes a capacitor providing a regulated voltage, a regulation switch for connecting the capacitor to a voltage source, and a regulation circuit for closing the regulation switch when the regulated voltage is below a first reference voltage. The voltage regulator also includes at least one ballast switch arranged in parallel with the regulation switch. The regulation circuit opens the regulation switch and closes the ballast switch during a starting phase of the regulator.

Abstract: A method for manufacturing memory points including control and floating gates, including the steps of: delimiting at the surface of the substrate an active region by insulation areas; forming a first insulating layer; opening a window in the first insulating layer to partially expose the entire width of the active region and a portion of the insulating areas; forming a second very thin insulating layer; depositing a first conductive material; forming a third insulating layer; and depositing a second conductive material, and further including a step of etching the first and second conductors and the third, second, and first insulating layers according to a same contour to expose the active region and the insulation areas in the vicinity of the borders between the active region and the insulation areas.

Abstract: An integrated circuit serial access type memory, notably in EEPROM technology, includes a data input (DI) and a data output (DO), a defined memory plane (MM) organized in memory words, as well as a set (LAT) of column registers, one such register being associated with at least one memory word of the memory. The memory includes a writing circuit and/or a reading circuit. The writing circuit operates, during an operation for writing a binary word in a given memory word (M0-M7), for loading the binary data of the binary word received in series at the data input (DI) directly into respective storage and switching latches (HV0-HV7) of the column register (R1) associated with the memory word (M0-M7). The reading circuit operates, during an operation for reading a binary word in a memory word, for reading successively the binary data stored in the memory cells of the memory word and for delivering directly, in serial form, each binary data read to the data output (DO) of the memory.

Abstract: A device for reading/rewriting a memory cell of a dynamic random-access memory organized in rows and columns, comprises, for each column, a first read/rewrite amplifier, and at least one second read/rewrite amplifier arranged in parallel with the first amplifier. A controller is provided for one of the amplifiers so that the amplifier is able to store the information contained in the memory cell for refreshing thereof, and so that the other amplifier is able to simultaneously perform read/rewrite accesses to and from the memory cell. One of the amplifiers may be permanently dedicated to operations for refreshing the memory cells and the other may be dedicated to read/write operations. Outputs of the amplifiers are connected to common output columns, and the controller includes an interrupter for the output of each amplifier to isolate the output from the corresponding output column and from the corresponding output of the other amplifier.

Abstract: A device for comparing two input signals includes a first comparator with differential outputs to whose inputs the signals are applied. The first comparator is followed by a second comparator delivering an output logic signal of the device. Each comparator includes at least one input differential stage, and each stage has two arms biased by a bias current generator. The comparison device may also include at least one additional current supply circuit associated with an arm of the input differential stage of the first comparator to copy the current of the arm and add it, with a multiplier factor, to the bias current of the input differential stage of the second comparator. This facilitates a corresponding switch-over.

Abstract: A column register of an integrated circuit memory, notably in EEPROM technology, is utilized in a method of writing a data word of 2P bits in the memory, where p is a non-zero whole number.

Abstract: A method of determining the time for polishing the surface of an integrated circuit wafer on a polishing machine. A sample wafer is fabricated to include at least one high plateau and at least one low plateau joined by a sudden transition. At least one initial profile is topographically scanned, and the surface of the sample wafer is polished at a particular polishing pressure for a particular polishing time. The final profile of the polished layer is topographically scanned in the corresponding area, and the initial and final topographical scans of the sample wafer are converted into Fourier series. The surface of the wafer to be polished is topographically scanned, and the topographic scan of the wafer to be polished is converted into a Fourier series. The time for polishing the wafer to be polished is calculated from the Fourier series and the average thickness to be removed.

Abstract: An electromagnetic transponder is provided that includes an oscillating circuit, an electronic circuit, a rectifying circuit, and a capacitive modulation circuit. The oscillating circuit includes an inductive clement and the electronic circuit includes a transmission circuit for transmitting digitally-coded information. The rectifying circuit is coupled to the oscillating circuit to provide a DC supply voltage to the electronic circuit, and the capacitive modulation circuit is coupled to both end terminals of the inductive element and to the reference potential of the electronic circuit. In a preferred embodiment, the capacitive modulation circuit includes two capacitors, with capacitor being coupled between one end terminal of the inductive clement and the reference potential and the other capacitor being coupled between the other end terminal of the inductive element and the reference potential.

Abstract: The present invention relates to a bidirectional switching circuit including, in series, a bidirectional switching element controllable to be turned off and turned on, and a bidirectional conduction element forming a dipole and automatically selecting the conduction direction.

Abstract: A probe tip card for enabling testing of components on a semiconductor wafer includes a printed circuit support card and a set of probe tips connected to the printed circuit support card. The probe tips are tilted with respect to the surface of the card and are held in a tilted position between an upper grid and a lower grid. The probe tip card allows for the testing of chips before they are diced from a semiconductor wafer.

Abstract: An electrical insulation circuit of the type connected between a peripheral circuit and a two-way bus. The electrical insulation circuit includes first and second optocouplers for transmitting differential signals in the peripheral circuit-to-bus direction, and third and fourth optocouplers for transmitting differential signals in the bus-to-peripheral circuit direction. The first and third optocouplers are associated with a first signal terminal on the peripheral circuit side and with a first data wire on the bus side, and the second and fourth optocouplers are associated with a second signal terminal on the peripheral circuit side and with a second data wire on the bus side. Further, the first and third optocouplers and the second and fourth optocouplers are connected such that the first and second optocouplers are off during transmission in the bus-to-peripheral circuit direction and the third and fourth optocouplers are off during transmission in the peripheral circuit-to-bus direction.

Abstract: A method for fabricating an integrated circuit. According to the method, a second dielectric layer is formed above a first dielectric layer, and holes and/or trenches are etched in the first and second dielectric layers. The holes and/or trenches are filled with metal in order to form electrical connection elements, and at least a third dielectric layer is formed. Holes and/or trenches are selectively etched in the third dielectric layer and the second dielectric layer with respect to the first dielectric layer and the elements, in order to control the depth of the etch. Additionally, there is provided an integrated circuit of the type having metallization levels separated by dielectric layers and metallized vias connecting lines of different metallization levels. The integrated circuit includes first and second metallization levels, first and second superposed dielectric layers located above the first metallization level, and a third dielectric layer located above the first and second dielectric layers.

Abstract: A method for managing interrupts in a microprocessor includes interrupts having a two-fold order of priority, i.e., a software priority and a hardware priority, wherein the microprocessor operates in two modes. During a first mode, the execution of an interrupt routine cannot be interrupted by the arrival of a new interrupt, even if it is a priority interrupt, unless this new interrupt is non-maskable. During a second mode, the execution of an interrupt routine is interrupted by the arrival of a priority interrupt. At the time of the execution of an interrupt, its software priority level is loaded into the state register of the microprocessor.

Abstract: The present invention relates to a frequency conversion receiver at low intermediary frequency including a first analog mixer of a received signal with a signal coming from a local oscillator at a first conversion frequency and a second analog mixer of the incoming signal with the signal coming from the local oscillator out of phase by 90°. The receiver further includes, on the digital side, circuitry for detecting a possible phase difference and a possible gain difference between the signals of the two paths, the first conversion frequency corresponding to the central frequency of the received channel, plus half the channel frequency band.

Abstract: A device for comparing two input signals includes a first comparator with differential outputs to whose inputs the signals are applied. The first comparator is followed by a second comparator delivering an output logic signal of the device. Each comparator includes at least one input differential stage, and each stage has two arms biased by a bias current generator. The comparison device may also include at least one additional current supply circuit associated with an arm of the input differential stage of the first comparator to copy the current of the arm and add it, with a multiplier factor, to the bias current of the input differential stage of the second comparator. This facilitates a corresponding switch-over.

Abstract: The amplifier includes an input amplifier stage, an output amplifier stage cascode-connected with the input amplifier stage, and a load stage connected to the output stage. The load stage includes a plurality of circuits each including a capacitive component and an inductive component having a Q greater than 10, and having respective different resonant frequencies. All the gain curves respectively associated with all the circuits have, to within a stated tolerance, the same maximum gain value at the resonant frequencies. The gain curves respectively associated with two circuits having respective immediately adjacent resonant frequencies overlap below a threshold 3 dB, to within a stated tolerance, below the maximum gain value.