Patents Assigned to STMicroelectronics S.A.
  • Normally-on bidirectional switch
    Patent number: 6323718
    Abstract: The present invention relates to a normally-on bidirectional switch, including, in parallel between two power terminals of the switch, a first cathode-gate thyristor, the anode of which is connected to a first power terminal, a second anode-gate thyristor, the anode of which is connected to a second power terminal, and a resistor in series with a controllable switch, the midpoint of this series association being connected to the respective gates of the two thyristors. The present invention also provides a monolithic integration of the switch.
    Type: Grant
    Filed: December 10, 1998
    Date of Patent: November 27, 2001
    Assignee: STMicroelectronics S.A.
    Inventors: Pierre Rault, Eric Bernier
  • Method of selecting a memory access line and an access line decoder for performing the same
    Patent number: 6324117
    Abstract: The invention proposes a method of selecting a determined access line of a serial access type integrated circuit memory, a determined access line being selectable among a determined group of access lines (AL0-AL7) of the same nature, for example a group of bit lines or a group of word lines, a line code on p bits being respectively associated to each access line of the group, which consists in pre-activating all the access lines of the group, then ofdeactivating progressively the other access lines as a function of the bits (Ai) of the line code of the access line to select received in series via the serial data input of the memory such that, in the end, only the access line to be selected remains activated.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: November 27, 2001
    Assignee: STMicroelectronics S.A.
    Inventors: Sébastien Zink, Bertrand Bertrand, David Naura
  • Method for the correction of a bit in a string of bits
    Publication number: 20010044922
    Abstract: A method for the correction of an erroneous bit in a string of bits includes providing, in the string of bits, for a first parity bit computed from the other bits of the string of bits at a point in time when the erroneous bit was valid. The correct value of the erroneous bit is computed by using the other bits of the string of bits comprising the parity bit. The erroneous bit is then replaced by its correct value. The method is applicable to error correction circuits in EEPROM memories.
    Type: Application
    Filed: December 15, 2000
    Publication date: November 22, 2001
    Applicant: STMicroelectronics S.A.
    Inventor: Francesco La Rosa
  • Process for determining an overflow to the format of the result of an arithmetic operation carried out on two operands
    Patent number: 6321248
    Abstract: A process is for determining an overflow to the format of the result of an arithmetic operation carried out by an arithmetic unit on two operands A and B and an input carry digit Cin. This process is executed in parallel to the processing done by the AU on operands A and B, before the AU has determined the result S of the operation.
    Type: Grant
    Filed: December 4, 1998
    Date of Patent: November 20, 2001
    Assignee: STMicroelectronics S.A.
    Inventors: Claire Bonnet, Sébastien Ferroussat, Didier Fuin
  • Self-aligned bipolar transistor manufacturing method
    Patent number: 6319786
    Abstract: The manufacturing of a bipolar transistor, including the steps of depositing a P-type polysilicon layer and an insulating layer on an N-type substrate; defining in said layers a base-emitter opening; performing a P-type doping and annealing to form a heavily-doped region partially extending under the periphery of the polysilicon layer; forming a spacer in an insulating material inside the opening; isotropically etching the silicon across a thickness greater than that of the heavily-doped region to form a recess; conformally forming by selective epitaxy a P-type silicon layer to form the transistor base layer; and depositing N-type heavily-doped polysilicon to form the transistor emitter.
    Type: Grant
    Filed: June 6, 2000
    Date of Patent: November 20, 2001
    Assignee: STMicroelectronics S.A.
    Inventor: Yvon Gris
  • Method and device for voltage multiplication
    Patent number: 6316986
    Abstract: At a charging phase, a capacitor (PC) is charged through two complementary charging transistors (TR1, TR2) connected in series to a first terminal (T1) of the capacitor (PC). At a voltage multiplication phase, an input voltage (Vdd) is delivered to the second terminal (T2) of the capacitor and an output voltage (Vout), increased with respect to the input voltage, is recovered at the first terminal (T1) of the, capacitor, and the capacitor is discharged during a discharging phase. During three phases, the substrate (BK2) of the charging transistor (TR2) directly connected to the first terminal (T1) of the capacitor is slaved to the source (S2) of this same charging transistor (TR2), while still keeping the source-substrate junction and the drain-substrate junction of this charging transistor (TR2) reverse-biased.
    Type: Grant
    Filed: May 25, 2000
    Date of Patent: November 13, 2001
    Assignee: STMicroelectronics S.A.
    Inventors: Richard Ferrant, Francois Jacquet
  • Vertical bipolar transistor including an extrinsic base with reduced roughness, and fabrication process
    Patent number: 6316818
    Abstract: The vertical bipolar transistor includes an SiGe heterojunction base formed by a stack of layers of silicon and silicon-germanium resting on an initial layer of silicon nitride extending over a side insulation region surrounding the upper part of the intrinsic collector. The stack of layers also extends on the surface of the intrinsic collector which lies inside a window formed in the initial layer of silicon nitride.
    Type: Grant
    Filed: June 1, 1999
    Date of Patent: November 13, 2001
    Assignees: STMicroelectronics S.A., Commissariat a l'Energie Atomique
    Inventors: Michel Marty, Alain Chantre, Jorge Regolini
  • Circuit for detecting electrical signals at a given frequency
    Publication number: 20010038341
    Abstract: The circuit for detecting the frequency of binary signals includes a circuit for detecting rising edges in the binary signals, a measuring circuit for measuring the period between the rising edges which supplies a logic state, and a shift register whose input latch stores the logic state. Also, the detecting circuit includes a shift circuit for shifting logic states of the shift register, and a decoding circuit for decoding logic states of the register, and which supplies a signal validating the signals. The detecting circuit can be used in contactless chip card readers.
    Type: Application
    Filed: April 18, 2001
    Publication date: November 8, 2001
    Applicant: STMicroelectronics S.A.
    Inventors: Ahmed Kari, Michel Bardouillet
  • Semiconductor package and method of manufacturing the same
    Patent number: 6312975
    Abstract: A semiconductor package having an encapsulation that encapsulates an integrated circuit chip and an external lead frame for the chip. Multiple connection leads project from the periphery of the encapsulation. At least one external face of the encapsulation is covered with a layer of electrically conductive material, and the conducting material layer has at least one lateral extension that electrically contacts at least one of the projecting connection leads. A method of manufacturing such a semiconductor package is also provided.
    Type: Grant
    Filed: January 26, 1999
    Date of Patent: November 6, 2001
    Assignee: STMicroelectronics S.A.
    Inventors: Rémi Brechignac, Alexandre Castellane
  • Memory with a reduced leakage current
    Patent number: 6314041
    Abstract: A SRAM including an array of memory cell lines and columns, each column being supplied between a high supply voltage and a low supply voltage, which includes at least one MOS transistor in series with each column, and circuitry for applying to the at least one MOS transistor a turn-off control signal to enter a stand-by mode, whereby the overall resistance of the column and of the at least one transistor increases in stand-by mode.
    Type: Grant
    Filed: April 20, 2000
    Date of Patent: November 6, 2001
    Assignee: STMicroelectronics, S.A.
    Inventor: Christophe Frey
  • Multistage operational amplifier with stability control
    Patent number: 6307438
    Abstract: A multistage operational amplifier includes a transconductor input stage, an output stage, and an intermediate stage. A first Miller capacitor is connected between the input and the output of the intermediate stage. A second Miller capacitor is connected between the input of the intermediate stage and an output of the output stage. A current mirror is connected to the output from the intermediate stage to draw a current therefrom.
    Type: Grant
    Filed: July 6, 2000
    Date of Patent: October 23, 2001
    Assignee: STMicroelectronics S.A.
    Inventor: Frédéric Goutti
  • Process and device for the baseband transcoding of digital information
    Patent number: 6307864
    Abstract: The symbols of a first code are represented by sign and magnitude bits in a manner analogous to the sign and magnitude bits representing the symbols of a second code. A memory stores digital samples partially representing coding pulses, and each pair of sign and magnitude bits is used to control a common shaping filter. The shaping filter uses the samples stored in the memory to generate a sampled digital signal representative of the analog signal transmitted over the telephone line.
    Type: Grant
    Filed: September 8, 1998
    Date of Patent: October 23, 2001
    Assignee: STMicroelectronics S.A.
    Inventors: Thierry Fensch, Gérald Kohlenberger, Céline Cornu
  • Reading device for integrated circuit memory
    Patent number: 6307797
    Abstract: A device for reading a memory including precharging circuits for precharging the inputs of a differential amplifier to a precharging voltage. The precharging voltage may be at an intermediate voltage level between a precharging voltage level of the bit lines and the voltage level of the logic supply voltage. This provides for a very fast build-up, during a following evaluation phase, of the output of the amplifier in a state corresponding to that of the cell being read. An internal detection circuit may also be included to detect an end of the precharging to stop the precharging circuit and activate the read current generator for the evaluation phase.
    Type: Grant
    Filed: November 28, 2000
    Date of Patent: October 23, 2001
    Assignee: STMicroelectronics S.A.
    Inventors: Richard Fournel, Laura Varisco
  • Memory incorporating column register and method of writing in said memory
    Patent number: 6307792
    Abstract: A column register of an integrated circuit memory, notably in EEPROM technology, is utilized in a method of writing a data word of 2p bits in the memory, where p is a non-zero whole number. The method includes the following steps: 1) erasing all the cells of the word; 2) loading 2q data in 2q high-voltage latches (HV1, HV3, HV5, HV7), and loading 2p−2q other data in the 2p−2q low-voltage latches (LV0, LV2, LV4, LV6); and 3) programming 2q cells of the memory (M0, M2, M4, M6) as a function of the data memorized in the 2q high-voltage latches; as well as repeating 2p−q−1 times the following steps: 4) loading, in the 2q high-voltage latches, of 2q other data that were loaded in the 2q low-voltage latches at step 2); and 5) programming 2q other cells of the memory (M1, M3, M5, M7) as a function of the data memorized in the 2q high-voltage latches.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: October 23, 2001
    Assignee: STMicroelectronics S.A.
    Inventors: Bertrand Bertrand, David Naura, Sébastien Zink
  • Method of manufacturing an avalanche diode with an adjustable threshold
    Patent number: 6306717
    Abstract: The present invention relates to a method of manufacturing an avalanche diode of determined threshold in a substrate of a first conductivity type with a low doping level, including the steps of diffusing in the substrate at least one first region of the first conductivity type; diffusing in the substrate a second region of the second conductivity type protruding from the first region. The opening of a mask of definition of the first region has a lateral extent smaller than the diffusion depth of the first region in the substrate, this lateral extent being chosen all the smaller as the desired avalanche threshold is high.
    Type: Grant
    Filed: March 30, 1999
    Date of Patent: October 23, 2001
    Assignee: STMicroelectronics S.A.
    Inventor: Isabelle Claverie
  • Regulating device
    Publication number: 20010030531
    Abstract: A regulating device for receiving a variable voltage and delivering a constant voltage includes a regulating element that includes a circuit for comparing the variable voltage with a reference voltage, a circuit for dividing the variable voltage by a factor, and a switching circuit for supplying the regulating element with a voltage equal either to the variable voltage or to the divided variable voltage. The switching circuit may be controlled by the comparison circuit in such a way that the regulating element is supplied with the variable voltage if a voltage condition is not satisfied and with the divided variable voltage if the voltage condition is satisfied.
    Type: Application
    Filed: December 28, 2000
    Publication date: October 18, 2001
    Applicant: STMicroelectronics S.A.
    Inventor: Laurent Micheli
  • Low electrical consumption voltage regulator
    Publication number: 20010030530
    Abstract: A voltage regulator includes a regulation MOS transistor and an amplifier providing an output for driving a gate of the regulation MOS transistor. The amplifier drives the gate based upon a difference between a reference voltage and a feedback voltage. The voltage regulator may further include a circuit for making the amplifier switch to a standby mode with low current consumption when the difference between the supply voltage and the output voltage of the regulator is below a first threshold. This is done while maintaining, at the gate of the regulation transistor, a voltage that keeps the regulation transistor on. The present invention is particularly applicable to the management of power supplies in portable telephones.
    Type: Application
    Filed: April 4, 2001
    Publication date: October 18, 2001
    Applicant: STMicroelectronics S.A.
    Inventor: Nicolas Marty
  • Device for synchronizing a reference event of an analog signal on a clock
    Patent number: 6304113
    Abstract: A device for synchronizing a reference event of an analog signal, which includes an analog-to-digital converter receiving an input signal, a register receiving the converter output, a phase-locked loop including an oscillator generating several phase-shifted clock signals of same period, a first clock signal clocking the register, a multiplexer receiving the other clock signals on respective inputs, the output of which clocks said converter, and an analysis circuit connected to control the multiplexer according to successive values of the register output.
    Type: Grant
    Filed: July 28, 2000
    Date of Patent: October 16, 2001
    Assignee: STMicroelectronics S.A.
    Inventor: Pierre Dautriche
  • Read only memory integrated semiconductor device
    Patent number: 6304480
    Abstract: A read only memory integrated semiconductor device includes at least one memory cell. The memory cell includes a storage transistor made within a semiconductor substrate and whose source is connected to ground. A word line is connected to the gate of the transistor. Only one of several bit lines may be connected to the drain of the transistor at a time.
    Type: Grant
    Filed: June 9, 2000
    Date of Patent: October 16, 2001
    Assignee: STMicroelectronics S.A.
    Inventor: Jean-Pierre Schoellkopf
  • Device to monitor the content and/or display of messages
    Patent number: RE37456
    Abstract: The period for which advertisements are displayed on display screens is monitored by coupling the displaying time with the time of a telephone call from a public telephone booth near the display panel. Preferably, the call made from this booth is paid with a pre-payment memory card. This memory card also has a memorizing zone in which it is possible to record an advertisement which is precisely the advertisement to be displayed.
    Type: Grant
    Filed: February 18, 1998
    Date of Patent: November 27, 2001
    Assignee: STMicroelectronics S.A.
    Inventor: Pierre Brisson