Patents Assigned to STMicroelectronics S.A.
  • Method of erasing a FAMOS memory cell and a corresponding memory cell
    Publication number: 20020176289
    Abstract: A FAMOS memory cell is electrically erased. The FAMOS memory cell may be electrically erased by applying to the substrate a voltage having a value at least 4 volts higher than the lower of a voltage applied to the source and a voltage applied to the drain. The voltage applied to the substrate is also less than a predetermined limit above which the memory cell is destroyed.
    Type: Application
    Filed: April 3, 2002
    Publication date: November 28, 2002
    Applicant: STMicroelectronics S.A.
    Inventors: Richard Fournel, Cyrille Dray, Daniel Caspar
  • Method of fabricating a vertical insulated gate transistor with low overlap of the gate on the source and the drain, and an integrated circuit including this kind of transistor
    Publication number: 20020177265
    Abstract: The vertical transistor includes, on a semiconductor substrate, a vertical pillar 5 having one of the source and drain regions at the top, the other of the source and drain regions being situated in the substrate at the periphery of the pillar, a gate dielectric layer 7 situated on the flanks of the pillar and on the top surface of the substrate, and a semiconductor gate resting on the gate dielectric layer. The gate includes a semiconductor block having a first region 800 resting on the gate dielectric layer 7 and a second region 90 facing at least portions of the source and drain regions and separated from those source and drain region portions by dielectric cavities 14S, 14D.
    Type: Application
    Filed: April 2, 2002
    Publication date: November 28, 2002
    Applicant: STMICROELECTRONICS S.A.
    Inventors: Thomas Skotnicki, Emmanuel Josse
  • Method and circuit for forming on-screen displays for overlay on a video image
    Patent number: 6486921
    Abstract: A method is provided for displaying an OSD on a video image. According to the method, values of pixels of the OSD are stored, and pixels of lines of the OSD that are to be displayed without processing are displayed by making direct use of a color look-up table. Additionally, pixels of lines of the OSD that are to be displayed after processing with a mathematical filter and/or that are required for computations associated with the mathematical filter are processed. In the processing step, the pixels of the lines to be processed are stored in the form of addresses that designate the memory lines of the color look-up table, the values of the pixels of the lines to be processed are obtained by an addressing of the color look-up table, and a mathematical filter is applied to the obtained values of the pixels to be processed.
    Type: Grant
    Filed: October 8, 1999
    Date of Patent: November 26, 2002
    Assignee: STMicroelectronics S.A.
    Inventor: Mark Vos
  • Sinusoidal signal multiplier circuit
    Publication number: 20020171460
    Abstract: A sinusoidal signal multiplier circuit produces an output sinusoidal signal substantially without any DC component. This sinusoidal signal multiplier circuit includes a first multiplication cell receiving a first sinusoidal signal at a first input and a second sinusoidal signal at a second input. The first multiplication cell delivers a first output signal. The sinusoidal signal multiplier circuit also includes a second multiplication cell, identical to the first multiplication cell, that receives the second sinusoidal signal at its first input and the first sinusoidal signal at its second input, and delivers a second output signal. The sinusoidal signal multiplier circuit also includes an adder circuit to add the first output signal and the second output signal to provide from the sinusoidal signal multiplier circuit an output signal substantially without any DC component.
    Type: Application
    Filed: March 19, 2002
    Publication date: November 21, 2002
    Applicant: STMICROELECTRONICS S.A.
    Inventor: Luc Garcia
  • Integrated inductance
    Publication number: 20020170743
    Abstract: An inductance device in monolithic structure is formed from a first metallization level layer of lower parallel conductive lines extending along the inductance pattern; next, on a second level, a set of vias is formed over each underlying conductive line being associated with at least two vias; and in a third metallization level, upper conductive lines interconnected to the underlying conductive lines by means of vias, the lower and upper conductive lines being shifted with respect to one another to ensure the electric continuity.
    Type: Application
    Filed: April 5, 2002
    Publication date: November 21, 2002
    Applicant: STMicroelectronics S.A.
    Inventor: Samuel Boret
  • Computer system with debug facility
    Publication number: 20020174385
    Abstract: A computer system for executing instructions having assigned guard indicators, comprises instruction supply circuitry, pipelined execution units for receiving instructions from the supply circuitry together with at least one guard indicator selected from a set of guard indicators, the execution unit including a master guard value store containing master values for the guard indicators, and circuitry for resolving the guard values in the execution pipeline and providing a signal to indicate whether the pipeline is committed to the execution of the instruction, and an emulator having watch circuitry for effecting a watch on selected instructions supplied to the execution pipeline and synchronising circuitry for correlating resolution of the guard indicator of each selected instruction with a program count for that instruction.
    Type: Application
    Filed: December 12, 2001
    Publication date: November 21, 2002
    Applicant: STMicroelectronics S.A.
    Inventors: Andrew Cofler, Laurent Wojcieszak, Arnaud Dehamel, Isabelle Sename
  • Voltage generation circuit of charge pump type, with a self-oscillating control circuit
    Patent number: 6483376
    Abstract: The present invention relates to a potential generation circuit of charge pump type, this circuit including at least two stages formed of capacitors and of circuitry for isolating or interconnecting the capacitors, to generate an output potential by charge transfer between the stages. The circuit is driven by two control potentials oscillating between a first and a second value. The circuit includes a self-oscillating control circuit to generate control potentials, to eliminate time delays between charge and discharge phases.
    Type: Grant
    Filed: September 2, 1998
    Date of Patent: November 19, 2002
    Assignee: STMicroelectronics S.A.
    Inventors: Philippe Bienvenu, Antoine Pavlin
  • Circuit for controlling a power MOS transistor and detecting a load in series with the transistor
    Patent number: 6483370
    Abstract: The detection of the presence of a load associated with a power MOS transistor integrated with its control circuit, using a delay determined taking into account the detection with respect to the occurrence of a turn-off control order of the power transistor, and where the filtering time is controlled with the power transistor switching time.
    Type: Grant
    Filed: July 19, 2000
    Date of Patent: November 19, 2002
    Assignee: STMicroelectronics S.A.
    Inventors: Philippe Bienvenu, Antoine Pavlin
  • Multiplexed flip-flop electronic device
    Publication number: 20020167973
    Abstract: A multiplexed flip-flop electronic device includes a decoder logic circuit for providing a first switching signal, and a control circuit for receiving a clock signal and for providing a gated clock signal forming a second switching signal. The electronic device further includes a multiplexing circuit having N inputs and an output, and a flip flop circuit. The flip-flop circuit includes a first switching stage connected between the N inputs and the output of the multiplexing circuit, and includes N switches being individually controlled by the first switching signal. A first buffer stage is connected to the output of the multiplexing circuit, and a second switching stage is connected to an output of the first buffer stage. The second switching stage is controlled by the second switching signal. A second buffer stage is connected to an output of the second switching stage.
    Type: Application
    Filed: May 8, 2002
    Publication date: November 14, 2002
    Applicant: STMicroelectronics S.A.
    Inventor: Thomas Alofs
  • Wideband differential amplifier comprising a high frequency gain-drop compensator device
    Publication number: 20020167356
    Abstract: A wideband differential amplifier includes a first differential stage connected to a Miller stage allowing an open-loop gain increase. The Miller stage includes a current source and a resistive-capacitive network causing a feedback into the current source. The feedback includes a portion of a Miller stage output signal having a high frequency range to move a bias point of the current source within the high frequency range. Thus, a gain of the Miller stage significantly increases towards the bias point.
    Type: Application
    Filed: May 13, 2002
    Publication date: November 14, 2002
    Applicant: STMicroelectronics S.A.
    Inventors: Claude Renous, Francois Van-Zanten
  • Differential amplifier comprising an unlocking device
    Publication number: 20020167357
    Abstract: A differential amplifier may include a first stage including a first transistor and a second transistor having the same polarity and assembled to constitute a differential amplifier. The first stage may be supplied by first and second mirror current sources. The differential amplifier may further include a common mode control circuit, which may include two inputs receiving a reference voltage VCM and a common mode voltage controlling the first and second mirror current sources, respectively. The differential amplifier may further include a Miller gain stage having inputs and for a setting gain-band product. The differential amplifier may further include an unlocking circuit, inserted between the common mode voltage and the Miller gain stage inputs, to cause the Miller gain stage to conduct on circuit start-up.
    Type: Application
    Filed: May 13, 2002
    Publication date: November 14, 2002
    Applicant: STMicroelectronics S.A.
    Inventor: Claude Renous
  • Frequency-modulated signal receiver with digital demodulator
    Publication number: 20020168028
    Abstract: A receiver of a frequency-modulated signal is provided. The receiver includes a frequency-transposition unit for lowering the frequency of the frequency-modulated signal, and a digital demodulator for regenerating a digital signal from the frequency-transposed signal. The frequency-transposition unit includes a local oscillator for generating a local oscillator signal used in lowering the frequency of the frequency-modulated signal. The frequency-transposed signal is sampled in the digital demodulator at the rate of a sampling signal, and the sampling signal is generated by the local oscillator of the frequency-transposition unit. In a preferred embodiment, the local oscillator includes at least one frequency-divider circuit that delivers the sampling signal. Also provided is a method for regenerating a digital signal from a frequency-modulated signal.
    Type: Application
    Filed: March 21, 2002
    Publication date: November 14, 2002
    Applicant: STMICROELECTRONICS S.A.
    Inventors: Marc Joisson, Luc Garcia, Marc Gens
  • Device for the detection of a high voltage greater than a supply voltage
    Patent number: 6480040
    Abstract: A device for detecting the application of a high voltage signal to an internal node of an integrated circuit includes a high-voltage divider circuit and a threshold detection circuit. The threshold detection circuit receives a signal given by the output of the divider circuit, and provides a threshold crossing detection signal at an output thereof based upon the signal crossing a threshold. The detection circuit is connected between the logic supply voltage and ground, and further includes a negative feedback loop. The negative feedback loop is connected to the output of the divider circuit to limit the voltage build-up of the high voltage signal at the output thereof after the crossing of the detection threshold by the signal.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: November 12, 2002
    Assignee: STMicroelectronics S.A.
    Inventor: Richard Fournel
  • Driver circuit for driving a plasma display panel driver module incorporating said circuit and method of testing such a module
    Patent number: 6480176
    Abstract: A driver circuit for driving a plasma display panel comprising a plurality of cells arranged in a matrix of lines and columns; comprising a set of driver output stages connected to line or column electrodes to which a first electrode of cells of a same line or a same column are connected, respectively. The driver circuit includes a detection device for detecting a short circuit between two or more of the outputs of the driver output stages. It allows to test for alignment faults in the flexible cable connecting together the driver module housing incorporating the driver circuit and the electrodes of the plasma display panel.
    Type: Grant
    Filed: September 27, 1999
    Date of Patent: November 12, 2002
    Assignee: STMicroelectronics S.A.
    Inventors: Céline Lardeau, Gilles Troussel, Eric Benoit
  • Power component state detector
    Patent number: 6479841
    Abstract: A detector of the state (on or off) of a vertical power component formed in a lightly-doped semiconductor substrate of a first conductivity type having a front surface and a rear surface. The region corresponding to the power component is surrounded with an isolating wall of opposite type to that of the substrate. This state detector is formed outside of said region and is formed with a vertical detection component, the state of which is switched by parasitic charges propagating outside of the isolating wall when the power component is on.
    Type: Grant
    Filed: November 2, 2000
    Date of Patent: November 12, 2002
    Assignee: STMicroelectronics S.A.
    Inventor: Jean-Michel Simonnet
  • Method for the calibration of an RF integrated circuit probe
    Patent number: 6480013
    Abstract: A method for the calibration of an RF integrated circuit probe comprising a step to determine the characteristics of the RF transmission lines of the probe by means of a vector network analyzer and standard circuits on silicon substrate. The standard circuits comprise contact pads corresponding by their layout to RF connection pads of the integrated circuits to be tested.
    Type: Grant
    Filed: February 7, 2000
    Date of Patent: November 12, 2002
    Assignee: STMicroelectronics, S.A.
    Inventors: Peter Nayler, Nicholas Smears, Philippe Planelle
  • Method of fabricating a vertical quadruple conduction channel insulated gate transistor, and an integrated circuit including this kind of transistor
    Publication number: 20020163027
    Abstract: The vertical insulated gate transistor includes, on a semiconductor substrate, a vertical pillar incorporating one of the source and drain regions at the top, a gate dielectric layer situated on the flanks of the pillar and on the top surface of the substrate, and a semiconductor gate resting on the gate dielectric layer. The other of the source and drain regions is in the bottom part of the pillar PIL and the insulated gate includes an isolated external portion 15 resting on the flanks of the pillar and an isolated internal portion 14 situated inside the pillar between the source and drain regions. The isolated internal portion is separated laterally from the isolated external portion by two connecting semiconductor regions PL1, PL2 extending between the source and drain regions, and forming two very fine pillars.
    Type: Application
    Filed: April 2, 2002
    Publication date: November 7, 2002
    Applicant: STMICROELECTRONICS S.A.
    Inventors: Thomas Skotnicki, Emmanuel Josse
  • Process for fabricating a component, such as a capacitor in an integrated circuit, and integrated-circuit component
    Publication number: 20020162677
    Abstract: Process for fabricating a component, such as a capacitor in an integrated circuit, and integrated component, in which process and component a first electrode is in the form of a cup; a layer made of a dielectric covers at least the wall of the first electrode; a second electrode fills the cup; a first electrical connection via lies above the second electrode; and a second electrical connection via lies laterally with respect to and at a predetermined distance from the first electrode and is connected to the first electrode.
    Type: Application
    Filed: May 1, 2002
    Publication date: November 7, 2002
    Applicant: STMICROELECTRONICS S.A.
    Inventors: Pascale Mazoyer, Christian Caillat
  • Word programmable EEPROM memory comprising column selection latches with two functions
    Publication number: 20020163832
    Abstract: An electrically programmable and erasable memory includes memory cells connected to word lines and to bit lines arranged in columns. Bit lines selection transistors are driven by bit lines selection signals. Column selection latches each includes a locking element for a column selection signal and a circuit for delivering a gate control signal which depends on the output of the locking element. Each column selection latch delivers, in addition to a gate control signal, a bit lines selection signal. This signal depends on the output of the locking element at least during programming and reading phases of the memory cells.
    Type: Application
    Filed: March 18, 2002
    Publication date: November 7, 2002
    Applicant: STMicroelectronics S.A.
    Inventors: Bertrand Bertrand, Mohamad Chehadi, David Naura
  • Power supply detection device
    Publication number: 20020163364
    Abstract: In an integrated circuit, a detection device detects a drop in the supply voltage of the core of the integrated circuit or an excessively slow build-up of this voltage with respect to a supply voltage of the input/output interface circuits of the integrated circuit. Outputs of the interface circuits are set to a high impedance state by the detection device to minimize their power consumption.
    Type: Application
    Filed: April 1, 2002
    Publication date: November 7, 2002
    Applicant: STMicroelectronics S.A.
    Inventors: Sylvain Majcherczak, Guy Mabboux