Abstract: A testing device for testing dynamic characteristics of an electronic circuit using serial transmissions. The circuit includes a multiplexing device and a demultiplexing device for implementing a serial link in the component or circuit. The testing device includes a transmitter for transmitting binary signals to the multiplexing device, a receiver for receiving binary signals from the demultiplexing device, and a link for selectively providing a coupling between the transmitter and the receiver. Additionally, a clock generator delivers a first clock signal to the transmitter and a second clock signal, which has a different frequency than the first clock signal, to the receiver. In one preferred embodiment, the clock generator includes a single programmable-frequency oscillator and a variable delay circuit. The programmable-frequency oscillator delivers the first clock signal and the variable delay circuit delays the first clock signal to deliver the second clock signal.

Abstract: A serial input/output memory is able to read data in the memory upon reception of a partial read address in which there are N least significant bits lacking to form a complete address. The read-ahead step includes: simultaneously reading the P first bits of M words of the memory having the same partial address; when the received address is complete, selecting the P first bits of the word designated by the complete address and delivering these bits at the serial output of the memory; reading P following bits of the word designated by the complete address during the delivery of P previous bits and delivering these bits at the serial output of the memory when the P previous bits are delivered.

Abstract: The present invention relates to a method of data transmission over an A.C. power supply line of a load to be cyclically powered, including organizing a switching of the A.C. supply voltage according to a coding of the data to be transmitted and outside cyclic load supply periods.

Abstract: A micro-pipeline type asynchronous circuit and a method for detecting and correcting soft error. The asynchronous circuit records in a first recording unit a signal output by a calculation unit and then records in a second recording unit the same signal delayed by at least the duration of the pulse of a soft error. The recorded signals then are compared in a comparer circuit. If they are identical, no soft error has been detected and the output signal is recorded after another delay that is longer than the pulse duration of the soft error, and a request signal is transmitted to a control unit of a next logic stage with a delay twice as long as the pulse duration of a soft error.

Abstract: Reference cells are refreshed in a non-volatile memory that includes a plurality of memory cells. A selected reference cell and a non-used memory cell are read simultaneously, and a signal read from the reference cell is compared to a signal read from the non-used memory cell. A refresh signal for refreshing the reference cell is supplied when the signal read therefrom is less than the signal read from the non-used memory cell.

Abstract: A device for reading from a capacitive memory cell, including a comparator of the voltage stored in the memory cell with respect to a reference value, which exhibits a high input impedance; a refreshment means distinct from the comparator, the refreshment means having a low output impedance and being controlled by the comparator to impose a refreshment voltage to the memory cell; and means for controllably connecting the refreshment means to the memory cell.

Abstract: A self-aligned double-polysilicon type bi-polar transistor with a heterojunction base comprises a semiconducting heterojunction region lying over an active region of a semiconductor substrate and over an isolating region delimiting the active region, and incorporating the intrinsic base region of the transistor. An emitter region situated above the active region and coming into contact with the upper surface of the semiconducting heterojunction region. A polysilicon layer forming the extrinsic base region of the transistor, situated on each side of the emitter region and separated from the semiconducting heterojunction region by a separation layer comprising an electrically conducting connection part situated just outside the emitter region. This connection part ensures an electrical contact between the extrinsic base and the intrinsic base.

Abstract: A method and apparatus for determining the distance separating an electromagnetic transponder from a terminal generating a magnetic field by a first oscillating circuit, the transponder including a second oscillating circuit, upstream of a rectifying circuit adapted to providing a D.C. voltage. The method includes storing a first information relative to the level of the D.C. voltage when the second oscillating circuit is tuned on a determined frequency; storing a second information relative to the level of the D.C. voltage after having caused a frequency detuning of the second oscillating circuit; and comparing the two stored pieces of information.

Abstract: A microprocessor comprises a central processing unit having an arithmetic and logic unit with two inputs and one input fed-back to one of the inputs through a data path. The arithmetic and logic unit performs arithmetic and logic operations on binary words temporarily stored within registers in the central processing unit. The central processing unit further includes a shift unit in the data path of the arithmetic and logic unit for performing operations to shift bits in the binary words applied thereto. A selection circuit selects a shift operation to be performed. An inverting circuit inverts the ordering of the bits in the binary words applied thereto, which are in the data path of the arithmetic and logic unit, and a selection circuit selects the inversion operation when the latter is required.

Abstract: A pulse-controlled analog flip-flop includes a charge element; a charge storage element connected to the charge element; an element for detecting the voltage across the storage element; and an element for discharging the storage element when the detection element has detected that the voltage across the storage element has reached a predetermined threshold.

Abstract: A method for the identification of electronic cards within an investigation zone includes encoding an identification number on M bits distributed into P blocks of Q bits assigned to each electronic card. Reconstruction of the block-by-block identification numbers is performed according to a tree-like iterative algorithm. In this iterative algorithm, each iteration includes a step for transmitting an interrogation message intended for certain electronic cards. Each iteration also includes a step for transmitting, by each of the electronic cards, a response message having a service bit in a narrow time window whose positioning in a sequence of 2Q successive identical windows indicates the value of an as yet unidentified block of bits of its identification number.

Abstract: A method for performing in a modular arithmetic coprocessor an integer division of a first binary data element by a second binary data element. The result is obtained by making an iterative loop of operations including an integer division of the first data element by a most significant word of the second data element. A test is performed to determine if the result of the division performed corresponds to a word of the final result sought. The first data element is modified by subtracting from it a data element produced by multiplying the second data element by the word of the final result sought that has been previously produced.

Abstract: A telephone line current amplifier comprises a current amplifying device comprising a first, second and third amplifier connected in cascade. The current from the third amplifier forms the output current of the current amplifying device. The current from the first amplifier subtracts from the current provided by the third amplifier, and the current from the second amplifier operates as a rectifier and outputs its current onto a power supply terminal. The power supply terminal is decoupled from ground via a capacitor. Another embodiment of the telephone line current amplifier comprises only two amplifiers if less severe distortion ratios are imposed.

Abstract: An integrated circuit fuse is formed on a substrate by etching a polysilicon, metal or alloy layer deposited thereon to include a central region, at the end of which are zones with electrical contacts. The central region has at least two first electrically parallel arms. A zone of intersection of the first two arms forms a point for focusing a fusing current which facilitates the fusing of the fuse by increasing local current density flowing through the integrated circuit.

Abstract: The detection of the presence of a load associated with a power MOS transistor integrated with its control circuit, using a delay determined taking into account the detection with respect to the occurrence of a turn-off control order of the power transistor, and where the filtering time is controlled with the power transistor switching time.

Abstract: A transistor manufacturing process includes the formation, on a layer (15) that will form the base of the transistor, of a stack of an SiGe alloy layer (16), a silicon oxide layer (17) and a silicon nitride layer (18), so as to form in this layer, a false emitter (20), to form, in the layer (15) that will form the base, an extrinsic base region (22) and to siliconize the surface of this extrinsic base region, to cover the extrinsic base region (22) and the false emitter (20) with a silicon dioxide layer (24) which is chemically and mechanically polished down to the level of the false emitter (20), to etch the false emitter (20) in order to form a window (25) and to form, in the window (25) and on the silicon dioxide layer (24), a polysilicon emitter (27). This process has particular application to manufacturing heterojunction bipolar transistors.

Abstract: A current source includes a master branch including a branch current fixing resistor, at least one slave branch, and a current mirror including a mirror transistor in each of the master and slave branches, respectively, to couple the branches. The current source may additionally include at least one of a first circuit for injecting in the current fixing resistor a current proportional to the master branch current and a second circuit for injecting in a degeneration resistor of the mirror transistor of the slave branch a current proportional to a current of the slave branch. The invention is particularly applicable to the manufacture of integrated circuits.

Abstract: An output clock signal is generated from a main clock signal having a predetermined main frequency and from a secondary clock signal generated by a quartz crystal. A frequency synthesizer is preprogrammed to generate two output clock signals whose respective frequencies are slightly greater than and slightly less than the frequency of the main clock signal. The synthesizer switches between the two output clock signals depending on the phase error between the selected output clock signal and the main clock signal.

Abstract: A regulated voltage generator provides different regulated voltages to an integrated circuit. The regulated voltage generator includes a bandgap reference circuit and at least one gain stage connected to an output thereof. The output voltage of the bandgap reference circuit varies as a function of temperature to compensate for variations in the gain stage made up of first and second transistors. A regulated voltage output by the regulated voltage generator is independent of temperature and of the supply voltage. The value of the regulated voltage is adjusted via a load resistor and via the first and second transistors along with an output transistor of the bandgap reference circuit.

Abstract: The invention is directed to a method of manufacturing an area of a first type of conductivity extending a depth into a semiconductor substrate and having a doping gradient as a function of the depth into the semiconductor substrate. The method comprises acts of providing a semiconductor substrate of the first type of conductivity; implanting nitrogen in an upper surface of the semiconductor substrate, with a dose in a range of between approximately 5.1013 and 5.1015 at./cm2, annealing the semiconductor substrate; and growing an epitaxial layer on the substrate of the first type of conductivity having a doping level lower than the semiconductor substrate.