Abstract: The present invention relates to a transmitter of an analog order over an A.C. supply line meant for a load, including a one-way conduction element in parallel with a resistive element having a value that is a function of the analog order to be transmitted.

Abstract: A processing unit is associated with a first FIFO-type memory and with a second FIFO-type memory. Each instruction for loading memory stored data into a register within the processing unit is stored in the first FIFO-type memory, and other operative instructions are stored in the second FIFO-type memory. An operative instruction involving the register is removed from the second FIFO-type memory if no loading instruction which is earlier in time, and intended to modify a value of the register associated with this operative instruction is present in the first FIFO-type memory. In the presence of such an earlier loading instruction, the operative instruction is removed from the second FIFO-type memory only after the loading instruction has been removed from the first FIFO-type memory.

Abstract: A current source includes a current mirror and a core connected together between two supply terminals. The current mirror comprises a pilot transistor and first and second recopy transistors. The core comprises first and second transistors and a resistance. The first transistor and the first recopy transistor are connected together to form a first branch. The resistance and the second recopy transistor are connected together to form a second branch. The pilot transistor and the second transistor are connected together to form a third branch. These branches are connected between the two supply terminals. The first transistor is linked to the second branch between the resistance and the second recopy transistor. The second transistor is connected to the first branch between the first core transistor and the first recopy transistor.

Abstract: The method is for transmitting data between two devices via a clock wire or line and at least one data wire or line. The clock wire is maintained by default on a logic value A, and each device is capable of tying the clock wire to an electric potential representing a logic value B that is the opposite of A. According to the method, both devices tie the clock wire to B when a datum is transmitted, the device to which the datum is sent does not release the clock wire while it has not read the datum, and the device sending the datum maintains the datum on the data wire at least until an instant when the clock wire is released by the device to which the datum is sent. The method is particularly applicable to communication between a microcomputer and a microprocessor.

Abstract: A voltage-switching device includes a high-voltage translator connected to a high-voltage node receiving either a low-voltage logic level or a high-voltage level as a function of a low-voltage/high-voltage mode control signal to provide at least one output signal as a function of this mode control signal and of a switching control signal. A voltage-level switching circuit is controlled by output signals from the high-voltage translator and by the mode control signal and the switching control signal for application, as output voltage levels, of either ground or the low-voltage logic level in low-voltage mode or the high-voltage level in high-voltage mode.

Abstract: An inductance structure arranged on a semiconductor substrate, including an inductance and a conductive plane arranged between the inductance and the substrate. The conductive plane is formed of several separate conductive elements, the connection of which is performed by conductive tracks connecting at least one conductive element to a contact point M of the conductive plane. Each of the conductive tracks is arranged so that the resultant of the electromotive forces induced in said conductive track by the inductance is substantially null.

Abstract: An A.C./D.C. converter including a filtering capacitor and further including a first branch essentially including a first rectifying circuit and a current limiting circuit; a second branch essentially including a second rectifying circuit, the series voltage drop of which is limited to that of the switches forming it; and a selection circuit for selecting one of the two rectifying circuits.

Abstract: The microarchitecture of the arithmetic unit includes two cascaded N bit adders to provide an N bits result in an accumulator. The arithmetic unit also includes a carry save adder, followed by an adder, which, along with the accumulator, are extended to N+1 bits. A circuit for determining the output carry value associated with the result is also provided.

Abstract: A microprocessor is for detecting an interrupt request during execution of a program, saving contextual data elements of the program being executed, sending an interrupt acknowledge signal, and jumping to an interrupt subroutine if the interrupt request is still present after saving the contextual data. Otherwise, the microprocessor resumes execution of the interrupted program.

Abstract: The invention relates to a process for protection of the grid of a transistor in an integrated circuit for production of a local interconnection pad straddling over the grid and the silicon substrate on which it is formed. The process consists of applying a double dielectric-conducting layer on the transistor grid into which a polysilicon layer is added in order to use the selectivity principle, which is large considering the etching of polysilicon with respect to the oxide in which the local interconnection pad is formed. Furthermore, with the process according to the invention, a silicidation treatment can be applied beforehand on the active areas of the transistor and the grid.

Abstract: An amplifier device with gain switching includes an amplifier, and a configurable load circuit including an inductive element. The configurable load circuit is capable of exhibiting two configurations having two different impedance values. A controllable switch is connected between the amplifier and the load circuit to select one of the two configurations of the load circuit. The load circuit includes two insulated-gate field effect load transistors connected in series, and which operate in a triode mode. The inductive element is connected in parallel with the pair of load transistors, and between a power supply terminal and the switching circuit.

Abstract: A method for designing a processor core is provided. Configuration registers are programmed by providing a cell configured at either one or zero for each bit of the configuration registers. Each configured cell is a latch with a data input and control signal inputs for receiving a direct resetting command and a direct setting command, and is configured at either one or zero by inhibiting either the direct resetting command or the direct setting command. Further, writing into the cells is permitted only in a test mode. Also provided is a method for designing and programming a processor core of the type having configuration registers. According to this method, a non-programmed processor core is designed by providing one vacant cell for each bit of the configuration registers. The vacant cell has the same abstract as both cells configured at one and cells configured at zero.

Abstract: The source, drain and channel regions are produced in a silicon layer completely isolated vertically from a carrier substrate by an insulating layer, and are bounded laterally by a lateral isolation region of the shallow trench type.

Abstract: A device for detecting a defective power supply connection in an integrated circuit includes a comparison circuit for comparing voltage levels of an input/output pad of the integrated circuit and an internal power supply line connected to a power supply pad of the integrated circuit. A pull-down or pull-up device is connected between the input/output pad and the internal power supply line.

Abstract: The sequential access memory array is able to store p words each of n bits. Such p test words each made up of n test bits are written in the memory array, the p test words are extracted sequentially and, for each current word extracted, the n test bits that compose it are compared sequentially with n respective expected data bits before extracting the next test word.

Abstract: A radiation hardened memory device includes active gate isolation structures placed in series with conventional oxide isolation regions between the active regions of a memory cell array. The active gate isolation structure includes a gate oxide and polycrystalline silicon gate layer electrically coupled to a voltage potential resulting in an active gate isolation structure that prevents a conductive channel extending from adjacent active regions from forming. The gate oxide of the active gate isolation structures is relatively thin compared to the conventional oxide isolation regions and thus, will be less susceptible to any adverse influence from trapped charges caused by radiation exposure.

Abstract: An operational amplifier includes an input stage, and a level-transforming stage with first and second arms. Each arm has at least one bipolar transistor. Input transistors are connected to the input stage and are connected together by their bases. At least one gain stage is connected to the transistor of the second transforming arm. A current terminal of the transistor on the first transforming arm is connected to its base by a bypass arm. In addition, the amplifier has a centering transistor connected by its base to the transistors on the arms of the transforming stage for controlling a current which conducts through the bypass arm.

Abstract: The present invention relates to a method of manufacturing integrated circuits including high and low voltage MOS transistors. This method includes steps of forming insulated gate structure forming lightly-doped drain/source regions, depositing an insulating layer; forming a mask above the gates of the high voltage transistors which extends laterally beyond said gates; etching the insulating layer to leave spacers on the edges of the low voltage transistor gates; implanting a dopant adapted to forming heavily-doped drain/source contact regions of the high and low voltage transistors; and forming in a self-aligned way a metal silicide layer on the drain/source contact regions of all transistors, as well as on the gate contacts of the low voltage transistors.

Abstract: A method is provided for forming an on-screen display (OSD) for overlay on a video image. According to the method, colors that are to be used to display the OSD are stored in a color look-up table, and a coefficient of transparency is assigned to each line of pixels of the OSD before overlaying the OSD on the video image. In a preferred method, the colors are stored in the color look-up table as three significant values representing chrominance and luminance for each pixel of the OSD, and the assigned coefficients of transparency are stored in a programmable register. This provides a substantial memory space gain in the color look-up table, and thus the range of available colors can be very wide. A device for forming an OSD for overlay on a video image is also provided. The device includes a color look-up table that stores a color for each pixel of the OSD, and a transparency programming register that assigns a transparency level to each line of pixels of the OSD.

Abstract: A method is provided for controlling a capacitive charge pump. The charge pump is regulated by a regulating voltage when the supply voltage is greater than the regulating voltage. When the supply voltage is less than a triggering voltage, which is less than or equal to the regulating voltage, the charge pump is automatically supplied between the supply voltage and ground. In one preferred method, the charge pump has a first supply terminal connected to the supply voltage and a second supply terminal that is automatically grounded when the supply voltage is less than the triggering voltage. Also provided is a capacitive charge pump device that includes a charge pump having first and second supply terminals, a voltage regulator delivering a regulating voltage, a switch connected between the second supply terminal and ground, and switch control circuitry for automatically controlling the switch.