Abstract: A memory device having a reading configuration and including a plurality of memory cells, arranged in rows and columns, memory cells arranged on the same column having respective first terminals connected to a same bit line and memory cells arranged on the same row having respective second terminals selectively connectable to a same word line; a supply line providing a supply voltage; a column addressing circuit and a row addressing circuit for respectively addressing a bit line and a word line corresponding to a memory cell selected for reading in the reading configuration. The column addressing circuit is configured to bias the addressed bit line corresponding to the selected memory cell substantially at the supply voltage in the reading configuration.

Abstract: A method of performing a Grover's or a Deutsch-Jozsa's quantum algorithm being input with a binary function defined on a space having a basis of vectors of n of qubits includes carrying out a superposition operation over input vectors for generating components of linear superposition vectors referred to a second basis of vectors of n+1 qubits. An entanglement operation is performed over components of the linear superposition vectors for generating components of numeric entanglement vectors. The method allows a non-negligible time savings because the entanglement operation does not multiply a superposition vector for an entanglement matrix, but generates components of an entanglement vector simply by copying or inverting respective components of the superposition vector depending on values of the binary function. An interference operation is performed over components of the numeric entanglement vectors for generating components of output vectors.

Abstract: A digital camera includes a sensor (205) for sensing an image and producing a first signal. A Bayer pattern producer (210) is coupled to the sensor and structured to produce a Bayer pattern from the first signal. The Bayer pattern is then split (212) into separate color channels. A color interpolator (214) is structured to perform a modification on only one of the color channels produced by the splitter (212). A compressor (220) then compresses the interpolated and non-interpolated color channels into a compressed image. An output interface (226) facilitates remote transmission of the compressed image over a communication channel. This communication may be made over a network to a server that operates in conjunction with the digital camera to perform certain functions, like image processing, manipulation, storage and communication, as directed by a user of the digital camera.

Abstract: A method and the related circuit protect against malfunctioning of the feedback loop in switching power supplies. More particularly, the circuit identifies a condition of excessively high voltage at the output. In one embodiment the circuit for the protection against malfunctioning of the feedback loop of a switching power supply comprises: circuitry that generates a voltage proportional to the output voltage of the switching power supply; a comparator for comparing the voltage proportional to the output voltage with a reference voltage; a counter coupled to the comparator and capable of supplying an output signal when said voltage proportional to the output voltage exceeds said reference voltage a threshold number of times; said output signal is indicative of a malfunctioning of the feedback loop.

Abstract: Voltage-boosting device having a supply input receiving a supply voltage, and a high-voltage output. The device is formed by a plurality of charge-pump stages series-connected between the supply input and the high-voltage output. Each charge-pump stage has a respective enabling input receiving an enabling signal. A control circuit formed by a plurality of comparators is connected to the high-voltage output and generates the enabling signals on the basis of the comparison between the voltage on the high-voltage output and a plurality of reference voltages, one for each comparator. The charge-pump stages are grouped into sets of stages, and the stages belonging to a same set receive a same enabling signal; thus, as many comparators as there are sets of stages are present.

Abstract: A multilayer metal supply rings structure of an integrated circuit comprises at least two parallel perimetral metal rails defined in metal layers of different levels, geometrically superposed one to the other. Each rail is constituted by using definition juxtaposed modules, each module defining on a metal layer parallel segments, longitudinally separated by a separation cut, of each rail, superposed rails of said multilayer structure constituting one supply node being electrically interconnected through a plurality of interconnection vias through dielectric isolation layers between different metal levels. A feature of the multilayer metal supply rings structure is that the segments of each of said perimetral metal rails modularly defined on each metal level belong alternately to one and another supply node upon changing the metal level. A process of defining a multilayer metal supply rings structure is also disclosed.

Abstract: A step-up converter based on an integrated transformer, comprising a self-resonating oscillator circuit that has inductive elements constituted by primary and secondary windings of at least one first transformer, the self-resonating oscillator circuit being powered by an external supply voltage.

Abstract: A semiconductor memory device includes a plurality of memory cells arranged according to a plurality of rows and a plurality of columns. The memory devices further includes a plurality of bit lines, each bit line being associated with a respective column of the plurality, and a selecting structure of the bit lines, to select at least one among the bit lines, keeping the remaining bit lines unselected. The memory device further includes a voltage clamping circuit structured to cause the clamping at a prescribed voltage of the unselected bit lines adjacent to a selected bit line during an access operation to the memory.

Abstract: A method is provided for fabricating a semiconductor device that includes a suspended micro-system. According to the method, a silicon porous layer is formed above a silicon substrate, and the silicon porous layer is oxidized. An oxide layer is deposited, and a first polysilicon layer is deposited above the oxide layer. The first polysilicon layer, the oxide layer, and the silicon porous layer are selectively removed. A nitride layer is deposited, and a second polysilicon layer is deposited. The second polysilicon layer, the nitride layer, the first polysilicon layer, and the oxide layer are selectively removed. The silicon porous layer is removed in areas made accessible by the previous step. Also provided is a semiconductor device that includes a suspended structure fixed to at least two walls through a plurality of hinges, with the suspended structure including an oxide layer, a first polysilicon layer, a nitride layer, and a second polysilicon layer.

Abstract: A device corrects the power factor in forced switching power supplies and includes a converter and a control device to obtain a regulated voltage on an output terminal. The control device comprises an error amplifier having an inverting terminal (Vout) and a non-inverting terminal receiving a reference voltage. The device includes first and second resistances coupled in series with a conduction element positioned between the first resistance and the inverting terminal of the error amplifier and a fault detector suitable for detecting the electrical connection of the conduction element with the output terminal and suitable for detecting an output signal of the second resistance. The fault detector is suitable for supplying a malfunction signal upon detecting an electric disconnection of the conduction element from the output terminal or when the output signal of the second resistance tends to zero.

Abstract: A method for reducing non-uniformity or topography variation between a cell array area and a peripheral circuitry area is used in a process for manufacturing semiconductor integrated non-volatile memory devices, wherein an intermediate stack of multiple layers is provided during the manufacturing steps of gates structures in both the array and circuitry areas. A thin stack comprising at least a thin dielectric layer and a third conductive layer is provided over a second conductive layer before the step of defining the control gate structures in the array and the single gates in the peripheral circuitry. This intermediate stack of multiple layers is used in order to compensate for thickness differences between the dual gate structures in the array and the single gate transistors in the peripheral circuitry.

Abstract: The optical communication module can be coupled to at least one optical fiber and includes at least one optoelectronic device, a base portion, and a cover portion which can be connected to the base portion to define an internal chamber to house the optoelectronic device. The cover portion includes at least one window to couple at least one optical signal between the at least one device and the optical fiber. The module further includes a plate, substantially transparent to the optical signal, having a first side facing the cover portion and a second side facing the internal chamber, the first plate substantially enabling sealing of the window. A shielding plate can be connected to the second side and provided with at least one opening substantially aligned with the window to enable passage of the optical signal.

Abstract: A method for manufacturing a semiconductor substrate of a first concentration type is described, which comprises at least a buried insulating cavity, comprising the following steps: forming on the semiconductor substrate a plurality of trenches, forming a surface layer on the semiconductor substrate in order to close superficially the plurality of trenches forming in the meantime at least a buried cavity in correspondence with the surface-distal end of the trenches.

Abstract: An optimized architecture to implement connections between logic blocks and routing lines in reconfigurable gate arrays including connection blocks to connect inputs and outputs of different logic elements by means of connection wires, each connection block including a single line of pass transistor switches; and a decoding stage to drive the pass transistor switch.

Abstract: A process for manufacturing a phase change memory cell, comprising the steps of: forming a resistive element; forming a delimiting structure having an aperture over the resistive element; forming a memory portion of a phase change material in the aperture, the resistive element and the memory portion being in direct electrical contact and defining a contact area of sublithographic extension. The step of forming a memory portion further includes filling the aperture with the phase change material and removing from the delimiting structure an exceeding portion of the phase change material exceeding the aperture.

Abstract: The method controls, in a feedback mode, a common collector or common drain amplifier, biased with a voltage applied on a bias node produced by a biasing circuit that generates a temperature compensated reference voltage from which the bias voltage applied on the bias node of the amplifier is derived. The quiescent voltage on the output node of the amplifier is made substantially independent from temperature by sensing the quiescent voltage on the output node, and adjusting the voltage applied on the bias node of the amplifier based upon the difference between the reference voltage and the sensed quiescent voltage for maintaining it constant.

Abstract: A switched capacitance circuit including: a switched capacitance section, capable of receiving as input a signal and carrying out a sampling of said signal, the section comprising at least one group of capacitors each of which has a terminal connected to a common node; at least an operational stage including at least an input terminal connected to said common node, the operational stage providing a current to said common node for charging said group of capacitors during a sampling time interval of said signal. The circuit further includes an auxiliary circuit connected to said common node and capable of being activated/deactivated by an enabling signal for injecting a further current into said common node and increasing the current provided to said common node during at least one time interval equal to a fraction of said sampling interval.

Abstract: The semi-conductor memory includes a memory device to store digital data being provided with a first number of intermediate output ports including a first intermediate output port. Furthermore, the memory includes a register block that can be selectively connected to the first intermediate output port to store data in the memory device and a second number of output ports including first and second output ports. The memory includes an interface device to receive strobe signals from the memory device, each being indicative of the presence of data on the at least one intermediate output port. This interface device, based on the strobe signals, controls the register block to provide the data stored in the register on the first and second output ports, by emulating a multi-port memory where the second number is greater than the first number.

Abstract: A reconfigurable control structure for CPUs comprises a first control unit with a first basic instruction set associated therewith, and a second control unit, with a second instruction set associated therewith. Associated with the second control unit is at least one programming element for rendering the second instruction set selectively modifiable. Also present is at least one circuit element for supplying instruction codes to be executed to the first control unit and to the second control unit, so that each instruction can be executed under the control of at least one between the first control unit or the second control unit according to whether the instruction is comprised in the first basic instruction set and/or in the second selectively modifiable instruction set.

Abstract: A combined decoder reuses input/output RAM of a turbo-code decoding circuit as alpha-RAM or beta-RAM for a convolutional code decoding circuit. Additional operational units are used for both turbo-coding and convolutional coding. An effective harware folding scheme permits calculation of 256 states serially on 8 ACS units.