Abstract: A current mirror includes at least a first and a second mirror transistors inserted between a first and a second voltage reference and connected to an input terminal and to an output terminal of the current mirror, respectively. The current mirror further includes a base current compensation block inserted between the input terminal and common control terminals of the first and second mirror transistors and connected to a voltage reference. The base current compensation block at least includes a bias current generator of a bias current and a first compensation transistor inserted, in series to each other, between the voltage reference and the input terminal, and a second compensation transistor inserted between the voltage reference and the common control terminals of the mirror transistors and having a control terminal connected to a control terminal of the first compensation transistor.

Abstract: A high-voltage switch has a high-voltage input terminal, receiving a high voltage, and an output terminal. A pass transistor, having a control terminal, is connected between the high-voltage input terminal and the output terminal. The output of a voltage-multiplying circuit of the charge-pump type is connected to the control terminal. The voltage-multiplying circuit is of a symmetrical type, has first and second charge-storage means, receiving a clock signal of a periodic type, and has a first circuit branch and a second circuit branch, which are symmetrical to one another and operate in phase opposition with respect to the clock signal.

Abstract: A system for scanning a frequency spectrum to detect usage thereof includes an ultra-wideband receiver for performing the scanning, and cooperates with a spectrum usage estimator module and a radio controller unit. The spectrum usage estimator module derives from the scanning performed via the ultra-wideband receiver information as to usage of individual bands in the frequency spectrum. The radio controller unit controls operation of a radio cognitive system as a function of the information as to usage of individual bands in the frequency spectrum as derived by the spectrum usage estimator module. The radio cognitive system operates over unused bands in the frequency spectrum.

Abstract: An apparatus for the conversion of a digital input signal into an analog output signal, the apparatus including a first circuit receiving the digital input signal that is representative of the analog output signal and suitable for producing a first signal on an output line, and a second circuit for supplying a second signal on the output line, in response to a further digital signal. The further digital signal is a function of external variables, and the union of the first and second signal on the output line forms the analog output signal.

Abstract: An LDMOS device includes elementary MOS cells. The gate structure of the elementary cell includes a first conductor material finger. The LDMOS device includes first metal stripes for contacting source regions, second metal stripes for contacting drain regions, and third metal stripes placed on inactive zones for contacting a material finger by forming a contact point. The contact point is formed by a first prolongation of the material finger for connecting with one of the third stripes. The third metal stripe includes at least one fourth metal stripe placed on a separation zone. The material finger has a second prolongation and the fourth metal stripe has a first prolongation to form an additional contact point.

Abstract: Multi-level programming allows for writing a first and a second bit in selected cells by separately programming the first bit from the second bit. Programming of the first bit determines a shifting from a first threshold level to a second threshold level. Programming of the second bit requires a preliminary reading to detect whether the first bit has been modified, performing a first writing step to bring the cell to a third threshold voltage if the first bit has been modified and performing a second writing step to bring the selected cell to a fourth threshold voltage different from the third threshold level if the first bit has not been modified. For increasing reading and program reliability, during preliminary reading of the second portion a reading result is forced to correspond to the first threshold level.

Abstract: The present invention describes a device for detecting the power of a first signal at a given frequency. The device comprises a first circuit means for detecting the envelope of the first signal and a second circuit means coupled to the first circuit means and suitable for generating a second signal proportional to the average of the envelope detected. The second signal is proportional to the square root of the average power of the first signal.

Abstract: The invention relates to a method for erasing non-volatile memory cells, and to a corresponding non-volatile memory device of the programmable and electrically erasable type implementing the method, and comprising a memory cell array organized in a row-and-column layout, and divided in array sectors, including at least one row decode circuit portion being supplied positive and negative voltages. The method is applied whenever the issue of the erase algorithm is negative, and comprises the following steps: forcing an incompletely erased sector into a read condition; scanning the rows of said sector to check for the possible presence of a spurious current indicating a fail state; identifying and electrically isolating the failed row; re-addressing from said failed row to a redundant row provided in the same sector; re-starting the erase algorithm.

Abstract: A sensing circuit is provided for sensing semiconductor memory cells. The sensing circuit includes at least one first circuit branch, a feedback-controlled circuit element in the first circuit branch, a current-to-voltage conversion circuit in the first branch, and at least one comparator. The first circuit branch is coupled to a memory cell to be sensed so as to be run through by a current corresponding to a memory cell state. The feedback-controlled circuit element controls a memory cell access voltage, and the current-to-voltage conversion circuit converts the current into a corresponding converted voltage signal that is indicative of the memory cell state. The comparator compares the converted voltage signal with a comparison voltage for discriminating among at least two different states of the memory cell. The converted voltage signal corresponds to a control signal of the feedback-controlled circuit element. Also provided is a method of sensing a memory cell.

Abstract: The invention relates to a system for controlling the power dissipated by a power stage working in mixed Linear/PWM mode, for driving an electromagnetic load, the power stage comprising a power amplifier incorporating a bridge-like circuit, with a half bridge controlled in PWM mode and another half bridge controlled in linear mode, respectively by a converter block and by an error amplifier and wherein the electromagnetic load is crossed by a current and generates an electromotive force, the control system further comprising a first amplifier of a voltage drop, calculated on a sensing resistance of the electromagnetic load, whose output signal is further applied by a second amplifier. Advantageously, according to the invention, the Linear half bridge is controlled directly by an input voltage drawn from an input node outside the current control loop.

Abstract: A sequential program-verify method is used in a non-volatile memory device including a plurality of memory cells each one for storing a logic value, the cells being arranged into a plurality of alignments. The method includes the steps of: writing a set of target values into a plurality of blocks of cells, the corresponding cells of each block belonging to a common alignment, verifying each block of cells in succession to assert a fault value for each alignment in response to a non-compliance of the value stored in the cell of the block belonging to the alignment with the corresponding target value, buffering the fault values, and in response to the verification of all the blocks of cells providing an indication of the alignments being defective according to the fault values.

Abstract: A pointer circuit for pointing to elements in at least one collection of elements comprises a base pointer for providing a first binary-coded value defining a first address of an element in the collection. The pointer circuit also comprises a binary shift circuit receiving the first binary-coded value provided by the base pointer and a second binary-coded value defining a shift value. The binary shift circuit combines the first and second binary-coded values to provide a third binary-coded value defining a second address of an element in the collection differing from the first address by the shift value. A shift-value generator fed by the first binary-coded value generates the second binary-coded value depending on the first binary-coded value, so that a generated shift value takes into account shift values corresponding to first binary-coded values preceding a current first binary-coded value in a prescribed first binary-coded value progression order.

Abstract: A row decoder for an electrically programmable NAND memory further includes a first means for keeping at least a control node of an addressed memory block charged at a select voltage. A second means decouples all select lines from a global select line. A third means provides an access voltage to the select line corresponding to an addressed memory block for enabling respective access elements and for providing an access inhibition voltage to the select lines corresponding to a non-addressed memory block. The first, second and third means are activatable in a testing operation.

Abstract: A multi-level flash memory device allows for a faster and more effective configuration of the operating parameters of the memory device for performing the different functioning algorithms of the memory The identification of an optimal configuration of the operating parameters of the memory device during testing is simplified by allowing for a one-time processing of configuration bits into algorithm-friendly data that are stored in an embedded ancillary random access memory at every power-on of the memory device This is done by executing a specific power-on algorithm code stored in the ancillary read only memory of the embedded microprocessor.

Abstract: A method of compressing a stream of pixel data relative a two-dimensional object, pixels of which are scanned by rows from a source device to a receiver device, includes defining an extended context window to include a pair of pixels following a last encoded pixel on the row being scanned and the respective triplets of neighboring pixels belonging to the preceding row. The method includes defining a first distinct context array of pixels of the extended context window for the pixel of the pair immediately following the last encoded pixel, and a second context array of pixels of the extended context window for the other pixel of the pair. An extended context value relative to each pixel of the pair is calculated, and the extended context value relative to a first pixel immediately following the last encoded pixel is compared with an extended threshold.

Abstract: A power amplification device includes an input for receiving a signal having a useful or desired frequency band, and power amplification circuitry of the delta-sigma type connected to the input. The power amplification circuitry exhibits an order greater than or equal to one in the useful frequency band, and an order greater than or equal to one outside the useful frequency band.

Abstract: A system-on-chip (SoC) architecture includes a plurality of blocks, each including a power control module to selectively control the power dissipated by the bloc. For each block, a power register is provided to receive power control instructions to selectively control the respective power control module. The system also includes a power control unit for writing respective power control instructions into the power control registers of the blocks, whereby the power dissipated is controlled individually and independently for each block under the centralized control of the power control unit. For each block, a power status register is also provided to receive status information concerning power control within the respective block. The power control unit reads the status instructions from such power status registers.

Abstract: In a process for the fabrication of integrated resistive elements with protection from silicidation, at least one active area (15) is delimited in a semiconductor wafer (10). At least one resistive region (21) having a pre-determined resistivity is then formed in the active area (15). Prior to forming the resistive region (21), however, a delimitation structure (20) for delimiting the resistive region (21) is obtained on top of the active area (15). Subsequently, protective elements (25) are obtained which extend within the delimitation structure (20) and coat the resistive region (21).

Abstract: A circuit for converting a direct current input voltage into an output voltage greater than the input voltage. The circuit includes a charge pump and a block for generating pulse signals of a predetermined frequency to be applied to a control input of the charge pump. The settling time, i.e. the time necessary for the output voltage to attain its operating value and to maintain it with a given precision, is reduced by providing the circuit with charge injection control via modulation of the duty cycle of the pulse signals as a function of the difference between the output voltage, or a predetermined fraction thereof, and a predetermined reference voltage and in such a manner as to reduce the settling time as the difference diminishes. The circuit includes a regulator that controls the charge pump based upon the predetermined reference voltage.

Abstract: A circuit verifies and substitutes a defective reference cell of a memory device that includes at least one reference current path including the reference cell and a decoding transistor connected in series. The circuit includes at least one redundant reference current path identical to the at least one reference current path and in parallel therewith. A connection circuit connects in a mutually exclusive way control terminals of the decoding transistor and reference cell of the at least one reference current path to a node or control terminals of the decoding transistor and reference cell of the at least one redundant reference current path to the node. The connecting is based upon a logic signal. A window comparator is coupled to the reference current path for comparing a current therein with a pair of upper and lower thresholds, and outputs the logic signal for the connection circuit based upon the comparison.