Abstract: A control system for the characteristic parameters of an active filter includes: a system for the determination of the technological distribution of the components that provides the information related to said technological distribution of the components; an elaboration system for said information related to said technological distribution of the components; an active filter including at least two programmable passive circuital elements receiving said information related to said technological distribution of the components; said elaboration system, being aware of the topology for said active filter, comprises means for determining the value for said at least two programmable passive circuital elements; means for correcting the value for said at least two programmable passive circuital elements according to the value of the information related to said technological distribution of the components; means for determining the programming values for said at least two programmable passive circuital elements.

Abstract: A circuit verifies and substitutes a defective reference cell of a memory device that includes at least one reference current path including the reference cell and a decoding transistor connected in series. The circuit includes at least one redundant reference current path identical to the at least one reference current path and in parallel therewith. A connection circuit connects in a mutually exclusive way control terminals of the decoding transistor and reference cell of the at least one reference current path to a node or control terminals of the decoding transistor and reference cell of the at least one redundant reference current path to the node. The connecting is based upon a logic signal. A window comparator is coupled to the reference current path for comparing a current therein with a pair of upper and lower thresholds, and outputs the logic signal for the connection circuit based upon the comparison.

Abstract: An integrated control and power driving system moves a read/write head carrying arm over the surface of a disk. The integrated control and power driving system is applicable to a spindle motor, a mass storage disk drive and a voice-coil motor, for example, and includes a first chip and a second chip. The first chip integrates the output power stages driving the motors, and has an interface for outputting feedback signals representing functioning conditions of the voice-coil motor and of the spindle motor, and for receiving digital control signals of the output power stages.

Abstract: A protection circuit for a control terminal of a power device of the type comprising at least one resistive element connected between at least one output terminal of a driver and the control terminal of the power device includes at least one turning-off transistor having its conduction terminals connected to the control terminal of the power device and to at least one output terminal of the driver, respectively. A control terminal is coupled to the control terminal of the power device through a second resistive element.

Abstract: A start-detection circuit and a stop-detection circuit detect the start condition and the stop condition in a data signal associated with a clock signal according to the IIC protocol. The start-detection circuit comprises: a first detector to produce a first reset signal when a trailing edge of the data signal is detected; a counter to count pulses of a reference signal when the first reset signal is received, and to produce an enabling signal when the number of pulses counted has reached a predefined number; a second detector to store the enabling signal when a trailing edge of the clock signal is detected. The stop-detection circuit comprises a third detector to produce a stop signal when a leading edge of the data signal is detected after the detection of a leading edge of the clock signal.

Abstract: A method is described for controlling fuel injection in an spontaneous ignition engine equipped with an electronically controlled fuel injection system and with an electronic control unit receiving engine quantities comprising the pressure in the combustion changer of the engine and closed-loop controlling the fuel injection system on the basis of the pressure in the combustion chamber, in which the pressure in the combustion chamber is determined as a function of engine kinematic quantities such as the engine speed and the crank angle and of the fuel injection law, which is defined by the quantity of fuel injected and by the crank angle at the start of injection.

Abstract: A switching power supply includes input terminals, which receive a first voltage, and a switching converter stage, provided with a first switching device. The power supply further includes a second switching device, connected between the input terminals and the switching converter stage, and an activation device, associated with the second switching device for controlling the second switching device so as to limit a second voltage applied to the switching converter stage.

Abstract: A power IGBT device is monolithically integrated to include an input terminal suitable to receive an input voltage and an output terminal suitable to supply a current having a limited and predetermined highest value. Such IGBT device includes an IGBT power element inserted between said output terminal and a supply reference. The power element has a control terminal connected to the input terminal through a control circuit that includes at least a transistor inserted between the control terminal and the supply reference voltage and a resistive element inserted between the input terminal and the control terminal.

Abstract: A method for sealing electronic devices formed on a semiconductor substrate includes forming a plurality of first electronic devices adjacent a first portion of the semiconductor substrate, with each first electronic device including a first region comprising at least one first conductive layer projecting from the semiconductor substrate. A first sealing layer is formed adjacent the first regions for sealing the plurality of first electronic devices. A protective layer is formed adjacent the first sealing layer. The protective layer is etched to form protective spacers adjacent sidewalls of the first regions. The method further includes forming a plurality of second electronic devices adjacent a second portion of the semiconductor substrate, with each second electronic device including a second region comprising a second conductive layer projecting from the semiconductor substrate.

Abstract: An integrated circuit includes a semiconductor substrate including first and second portions, with first electronic devices adjacent the first portion. Each first electronic device includes a first region comprising at least one first conductive layer projecting from the semiconductor substrate. First protective spacers are adjacent sidewalls of the first regions of the first electronic devices. The first protective spacers are defined by first and second sealing layers adjacent one another. Second electronic devices are adjacent the second portion of the semiconductor substrate. Each second electronic device includes a second region comprising a second conductive layer projecting from the semiconductor substrate. Second protective spacers are adjacent sidewalls of the second regions of the second electronic devices. The second protective spacers are defined by other portions of the second sealing layer. The second sealing layer has a thickness less than a thickness of the first sealing layer.

Abstract: A control circuit for a DC/DC converter has a linear-control loop, which receives a quantity to be controlled and a first reference quantity, and generates a modulation value. A nonlinear modulation unit is activated in presence of a variation of the quantity to be controlled higher than a preset intervention threshold and modifies in a nonlinear way the reference quantity supplied to the linear-control loop. In the case of large variation and of preset sign of the quantity to be controlled, the linear-control loop is deactivated, a signal for switching-off of the DC/DC converter is initially generated, and then a false steady-state-modulation value is supplied to the DC/DC converter.

Abstract: A multi-standard transmitter includes a differential stage that includes a current generator transistor; first and second transistors connected between a first node and the generator transistor and having respective control terminals connected to a first input terminal, the first and second transistors being interconnected at a first output terminal; third and fourth transistors connected between the first node and the generator transistor and having respective control terminals connected to a second input terminal, the third and fourth transistors being interconnected at a second output terminal; and first and second resistances connected between the first and second output terminals and interconnected at a second node. The transmitter includes a selective enabling circuit connected to the first and second nodes, and to a third node corresponding to a control terminal of the generator transistor.

Abstract: A sensing circuit (120) for sensing currents, including: a measure circuit branch (132i), having a measure node for receiving an input current (Ic) to be sensed, for converting the input current into a corresponding input voltage (V?); at least one comparison circuit branch (132o), having a comparison node for receiving a comparison current (Igs), for converting the comparison current into a corresponding comparison voltage (V+); and at least one voltage comparator (140) for comparing the input and comparison voltages, and a comparison current generating circuit (N3s, 135; N3s, 135?; N3s, 135?) for generating the comparison current based on a reference current (Ir). The comparison current generating circuit includes at least one voltage generator (135; 135?; 135?). A memory device using the sensing circuit and a method are also provided.

Abstract: A process for manufacturing phase change memory cells includes the step of forming a heater element in a semiconductor wafer and a storage region of a phase change material on and in contact with the heater element. In order to form the heater element and the phase change storage region a heater structure is first formed and a phase change layer is deposited on and in contact with the heater structure. Then, the phase change layer and the heater structure are defined by subsequent self-aligned etch steps.

Abstract: A low supply voltage memory device includes a first supply pin and a second supply pin for the connection to a first supply voltage source (VDD) and to a second supply voltage source (VDDQ). The device may include a memory and at least one booster overlapped by way of a “system in package” system and in particular with “stacked-die” technology. This booster may be connected to the memory by way of a plurality of discrete components.

Abstract: A variable impedance circuit includes at least one fixed resistance and a plurality of transistors between a first and a second terminal. The transistors belonging to the plurality of transistors are arranged parallel to one another and parallel to the resistance and are controllable by a plurality of control signals different from one another and configured in such a way as to obtain a total impedance between said first and second terminals that is substantially variable in a continuous manner.

Abstract: A method and related system for performing fuzzy procedures in processing devices. The method provides for calculating a degree of activation of a fuzzy proposition represented by input values having a fuzzy set associated to a triangular or trapezoidal membership function. The membership function is defined by a defined range of the input values and by an abscissa of the maximum value assumed by said membership. The method includes storing solve values corresponding to the range of definition and to the abscissa of the maximum value. The degree of activation is calculated as a function of the stored solve values, and storing of solve values includes storing the values measured on the abscissa and further at least one value measured on the ordinate corresponding to the membership function.

Abstract: A sense amplifier for reading a non-volatile memory cell includes a bitline current path connected to a non-volatile memory cell to be read, and a reference current path connected to a reference memory cell. A current mirror includes an input transistor and a corresponding input node, and an output transistor and a corresponding output node. The current mirror converts currents in the reference current path and the bitline current path to respective voltages on the input and output nodes. An equalization circuit equalizes the voltages on the input and output nodes of the current mirror and is activated by a command signal. The equalization circuit includes a switch controlled by the command signal, and a diode-connected load transistor connected in parallel to the output transistor of the current mirror and connected to the output node thereof through the switch.

Abstract: The on resistance per unit area of integration of a DMOS structure is reduced beyond the technological limits of a mask that is defined based upon the continuity of a heavily doped superficial silicon region along the axis of the elongated source island openings through the polysilicon gate layer in the width direction of the integrated structure. The mask no longer needs to be defined with a width (in the pitch direction) sufficiently large to account for the overlay of two distinct and relatively critical masks. These two masks are the source implant mask and the body contacting plug diffusion implant contact opening mask.

Abstract: A method and control device is used for testing electronic memory devices. The method comprises loading test data and/or instructions into a control logic circuit portion associated with a matrix array of memory cells and integrated storage circuitry. According to the invention, a test operation control device is used temporarily instead of the control logic, the test operation control device being external of and connected detachably to the memory device. Advantageously, the test operation control device is a matrix cell array external of the memory.