Abstract: In a multi-channel amplifier switching from a single-ended to a bridge configuration, one of the two operational amplifiers of the output bridge structure of each channel is kept at the design reference voltage (typically to half the supply voltage) for as long as the other operational amplifier of the output bridge structure does not begin to saturate and by connecting in common the gate nodes of the P-type MOS transistors and the gate nodes of the N-type MOS transistors of the output half bridge stages of all the operational amplifiers of the output bridge pairs of all the channels that are eventually configured to function as voltage reference buffer, when configuring the multi channel amplifier to function in a single-ended configuration.

Abstract: A bipolar power transistor does not include integration of a Zener diode electrically connected between the base and collector for limiting the collector voltage. The power transistor is formed in a substrate, and includes an equalization diffusion and an auxiliary diffusion forming a P-N junction along a perimeter of the substrate An equalization conduction layer is in contact with the equalization diffusion and the auxiliary diffusion for electrically shorting the P-N junction.

Abstract: The driving voltage of the motor is incremented a quantity proportional to the speed of the motor according to a proportionality factor that is adjusted to compensate the back electromotive force. A method includes open-loop voltage control of a DC motor having a certain design speed constant, through a driving signal that is determined for imparting a certain acceleration to the motor and by generating a driving voltage of an output power stage to which the winding of the motor is connected as a function of the driving signal.

Abstract: An electric motor controller controls the currents flowing through the phase windings of an electric motor. The electric motor controller includes driving stages for driving respective phase windings of the motor and a memory for storing samples of reference signals. The driving stages force currents corresponding to the reference signals through a respective phase winding of the motor. The electric motor controller includes circuitry to determine subdivision degree intervals of an electric rotation and circuitry for comparing one of the currents flowing through the respective phase windings of the motor with at least one of the samples of the respective reference signal in at least one portion of each one of the degree intervals.

Abstract: A method for manufacturing circuit structures integrated in a semiconductor substrate that includes regions, in particular isolation regions, includes the steps of:—depositing a conductive layer to be patterned onto the semiconductor substrate;—forming a first mask of a first material on the conductive layer;—forming a second mask made of a second material that is different from the first and provided with first openings of a first size having spacers formed on their sidewalls to uncover portions of the first mask having a second width which is smaller than the first;—partly etching away the conductive layer through the first and second masks such to leave grooves of the second width;—removing the second mask and the spacers; and—etching the grooves through the first mask to uncover the regions provided in the substrate and form conductive lines.

Abstract: A method for testing a memory device having plural memory elements includes performing a succession of operations including: a) writing a test datum into the memory elements according to a first scanning sequence; b) accessing each memory element according to the first scanning sequence, reading a content thereof, comparing the read content to the test datum, and writing thereinto the test datum complement; c) accessing each memory element according to a second scanning sequence, reading a content thereof, comparing the read content to the test datum complement, and writing thereinto the test datum; d) accessing each memory element according to the second scanning sequence, reading a content thereof, comparing the read content to the test datum, writing thereinto the test datum complement, and reading again the content thereof and comparing the read content to the test datum complement.

Abstract: An optoelectronic module includes a first sub-module and a second sub-module. The first sub-module has a surface with a cavity formed therein, and includes an integrated waveguide provided with a first optical port accessible from the cavity. The second sub-module faces the first sub-module. A metallic wall extends from the first sub-module to the second sub-module, and surrounds the cavity to define a hermetically closed chamber. An optoelectronic device is coupled to at least one of the first and second sub-modules, and is included in the chamber. The optoelectronic may comprise a second optical port coupled to the first optical port in the first sub-module.

Abstract: A power conversion device includes a first and second input terminal for connection to a transformer winding and at least an output terminal. A first and second synchronous rectifier are associated with the first and second input terminals, respectively. An inductor within an output stage is connected between the first input terminal and the output terminal. A driving circuit includes first and second output terminals connected to respective control terminals of the first and second synchronous rectifiers. An adjustable threshold control block is connected between the first and second input terminals and is connected to the inductor. The control block is enabled responsive to a control signal on the first output terminal of the driving circuit. The control block operates to clamp the voltage of the first input terminal to a preset value during at least a dead time period of the device operation.

Abstract: The described analog-digital converter comprises quantization means having an input for receiving an analog quantity to be converted, a register having an output for providing a digital quantity corresponding to the analog quantity, a timing pulse generator and logic means connected to the quantization means, the register and the timing pulse generator and capable of responding to a conversion request signal by activating the quantization means in such a manner as to make them carry out predetermined operations timed by the timing pulses and load into the register the digital quantity to be provided at the output.

Abstract: An oversampling electromechanical modulator, including a micro-electromechanical sensor which has a first sensing capacitance and a second sensing capacitance and supplies an analog quantity correlated to the first sensing capacitance and to the second sensing capacitance; a converter stage, which supplies a first numeric signal and a second numeric signal that are correlated to the analog quantity; and a first feedback control circuit for controlling the micro-electromechanical sensor, which supplies an electrical actuation quantity correlated to the second numeric signal.

Abstract: A method and an equalizer circuit equalize signals transmitted on a line having an attenuation. The equalizer circuit includes: an analogical adaptive filter applied in series with the line and includes plural transconductance filters each having a bias current. The adaptive filter has a pole and a zero each having a frequency position in the working band that is variable in response to the bias current. The equalizer circuit includes a retroaction circuit applied to the output of the filter and able to vary the bias current according to the varying of the attenuation of the line. The bias current of the transconductance filters has a prefixed value and is made to vary at the increasing of the attenuation so that the pole is moved toward high frequencies and the zero is moved toward low frequencies.

Abstract: A redundancy scheme for a memory integrated circuit having at least two memory sectors and, associated with each memory sector, a respective memory location selector for selecting memory locations within the memory sector according to an address. The redundancy scheme comprises at least one redundant memory sector adapted to functionally replace one of the at least two memory sectors, and a redundancy control circuitry for causing the functional replacement of a memory sector declared to be unusable by one of the at least one redundant memory sector; the redundancy control circuitry detects an access request to a memory location within the unusable memory sector and diverts the access request to a corresponding redundant memory location in the redundant memory sector. Associated with each memory location selector, respective power supply control means are provided adapted to selectively connect/disconnect the associated memory location selector to/from a power supply distribution line.

Abstract: A NAND flash memory device includes a matrix of memory cells each having a threshold voltage. The matrix includes an individually erasable sector and is arranged in plural rows and columns with the cells of each column arranged in plural strings of cells connected in series. The memory device includes logic that erases the cells of a selected sector, and restoring logic that restores the threshold voltage of the erased cells. The restoring logic acts in succession on each of plural blocks of the sector, each block including groups of one or more cells. The restoring logic reads each group with respect to a limit value exceeding a reading reference value, programs only each group wherein the threshold voltage of at least one cell does not reach the limit value, and stops the restoring in response to reaching the limit value by at least one set of the groups.

Abstract: The present invention relates to a non volatile memory device architecture, for example of the Flash type, incorporating a memory cell array and an input/output interface to receive memory data and/or addresses from and to the outside of the device. The interface operates generally according to a serial communication protocol, but it is equipped with a further pseudo-parallel communication portion with a low pin number incorporating circuit blocks for selecting the one or the other communication mode against an input-received selection signal.

Abstract: A single-loop differential switched-capacitor sigma-delta converter has a three stage double-sampling architecture with reduced current consumption. The converter is stable for large input dynamics, which makes it suitable for RF applications. The three-stage multi-bit double-sampled architecture has a single-loop architecture in which all integrators are included in a same feedback loop. This has been made possible based upon the type of integrators that are connected in cascade. Functioning of the converter is less sensitive to nonlinearities of the operational amplifiers of the integrators.

Abstract: A vertical MOSFET transistor is formed in a body of semiconductor material having a surface. The transistor includes a buried conductive region of a first conductivity type; a channel region of a second conductivity type, arranged on top of the buried conductive region; a surface conductive region of the first conductivity type, arranged on top of the channel region and the buried conductive region; a gate insulation region, extending at the sides of and contiguous to the channel region; and a gate region extending at the sides of and contiguous to the gate insulation region.

Abstract: A non-volatile memory device is proposed. The non-volatile memory device includes a flash memory and means for executing external commands, the external commands including a first subset of commands for accessing the flash memory directly; the memory device further includes a programmable logic unit and means for storing program code for the logic unit, the external commands including a second subset of at least one command for causing the logic unit to process information stored in at least one portion of the flash memory under the control of the program code.

Abstract: A circuit is provided for controlling a minimum operating voltage of an integrated control circuit of a switching power supply. The circuit includes at least one switch for switching the minimum operating voltage from a first voltage value to a second voltage value under conditions of low or null load of the switching power supply, and for switching the minimum operating voltage from the second voltage value to the first voltage value if the load of the switching power supply is greater than a predetermined load and the supply voltage is greater than the first voltage value. The minimum operating voltage can assume at least the first voltage value and the second voltage value, and the first voltage value is greater than the second voltage value. Also provided is a method for controlling a minimum operating voltage of an integrated control circuit of a switching power supply.

Abstract: A non-volatile memory electronic device is integrated on a semiconductor and is of the Flash EEPROM type with an architecture of the NAND type including at least one memory matrix organized in rows or word lines and columns or bit lines of memory cells and with at least one associated row decoding circuit portion. Advantageously, the matrix includes at least one logic sector with pairs of rows or word lines being short-circuited with each other and referring to a respective biasing terminal, one for each pair, and in that the row decoding circuit portion includes a single select block which controls a single multiplexer for the logic sector for the regulation of the signals applied to the biasing terminals.

Abstract: A variable-gain amplifier includes an amplifier stage; an attenuating network receiving an input signal; a plurality of transconductance stages, connected between respective nodes of the attenuating network and the amplifier stage, wherein each of the transconductance stages has a differential circuit, configured to supply differential currents to the amplifier stage; and a gain-control circuit for controlling the transconductance stages according to an electrical control quantity. Each of the transconductance stages further includes a current-divider circuit associated to the differential circuit and controlled by the gain-control circuit so as to divide the differential currents between the amplifier stage and a dispersion line proportionally to the control quantity.