Abstract: A method for data transfer between two semi-synchronous clock domains in a System on Chip (SoC) includes first and second integrated processors or circuits respectively operating at first and second clock frequencies The SoC includes a phase for detecting, for each frequency ratio between the first and second clock frequencies, a maximum rate of the data transfer, with the rate being a function of all the possible input and output delays supported by the SoC. This is dependent on the parameters of the SoC. There is also a phase for programming a generic frequency converter between the first and second integrated processors for the data transfer, and a phase for scheduling the data transfer between the semi-synchronous clock domains.

Abstract: A low area architecture for embedded programming flash memory portions in microcontrollers is based on substitution of the ROM/RAM/CORE functionality with a digital ISP controller implemented in a finite state machine and a standard interface. After connecting ports of the embedded programming flash memory portion and releasing a RESET pin, the microcontroller enters a particular operating mode and is managed by the digital ISP controller instead of the CORE. The ROM is not required to set up the microcontroller, and as a consequence, transfer of the boot program from the ROM to the RAM is not requested for subsequent execution.

Abstract: A pipeline structure is provided for use in a digital system. The pipeline structure includes stages arranged in a sequence from a first stage for receiving an input of the pipeline structure to a last stage for providing an output of the pipeline structure. At least one intermediate stage is interposed between the first stage and the last stage. The pipeline structure also includes a phase shifting circuit for generating at least one local clock signal for controlling the at least one intermediate stage. The first stage and the last stage are controlled by a main clock signal, the at least one local clock signal is generated from the main clock signal, and the main clock signal and the at least one local clock signal are out of phase. Also provided is a method of operating a pipeline structure that includes stages arranged in a sequence.

Abstract: A phase difference detector adapted to generating a signal indicative of a phase difference between a first signal and a second signal, comprising: a first bistable element clocked by the first signal and having a first output signal, and a second bistable element clocked by the second signal and having a second output signal; means for determining the variation of the signal indicative of the phase difference, responsive to the first and second output signals, and a reset circuit having a first and a second inputs respectively connected to the first and second output signals and adapted to determine the resetting of the first and second bistable elements in response to the attainment of a respective prescribed state by the first and the second output signals. The first and second inputs of the reset circuit are substantially symmetrical to each other from the point of view of an input impedance associated to each of them.

Abstract: Described herein is a method for compressing a sequence of repetitive data, which uses in combination one or more words with a format for non-compressible data and one or more words with a format for compressible data, in which a word with a format for non-compressible data is made up of a set of bits, in which the most significant bit is set at the logic value “1” and the remaining bits are the bits of a non-compressible datum to be encoded, whilst a word with a format for compressible data is made up of a set of bits, in which the most significant bit is set at a the logic value “0”, the next five most significant bits indicate the total number of subsequent words which encode the sequence of repetitive data, and the remaining eleven bits indicate the number of times that the words indicated by the preceding five most significant bits are repeated.

Abstract: A packaging structure for optoelectronic components is formed by a first body, of semiconductor material, and a second body, of semiconductor material, fixed to a first face of said first body. A through window is formed in the second body and exposes a portion of the first face of the first body, whereon at least one optoelectronic component is fixed. Through connection regions extend through the first body and are in electrical contact with the optoelectronic component. The through connection regions are insulated from the rest of the first body via through insulation regions. Contact regions are arranged on the bottom face of the first body and are connected to said optoelectronic component via the through connection regions.

Abstract: In a data-input device an actuator element that can be manually actuated, and a sensor mechanically coupled to the actuator element. The sensor is formed in a body of semiconductor material housing a first sensitive element, which detects the actuation of the actuator element and generates electrical control signals. The first sensitive element is a microelectromechanical pressure sensor, formed by: a cavity made within the body; a diaphragm made in a surface portion of the body and suspended above the cavity; and piezoresistive transducer elements integrated in peripheral surface portions of the diaphragm in order to detect its deformations upon actuation of the actuator element.

Abstract: A process for manufacturing an integrated differential pressure sensor includes forming, in a monolithic body of semiconductor material having a first face and a second face, a cavity extending at a distance from the first face and delimiting therewith a flexible membrane, forming an access passage in fluid communication with the cavity, and forming, in the flexible membrane, at least one transduction element configured so as to convert a deformation of the flexible membrane into electrical signals. The cavity is formed in a position set at a distance from the second face and delimits, together with the second face, a portion of the monolithic body. In order to form the access passage, the monolithic body is etched so as to form an access trench extending through it.

Abstract: A method is provided for patterning a wafer comprising at least one substrate for the manufacture of an integrated circuit. The method comprises: etching at least one portion of the substrate with a reactive gas plasma to obtain an optical emission signal, resulting from the products of the reaction between the plasma and the substrate and having a predetermined spectral fingerprint; carrying on the etching of the substrate up to a predetermined end point; and monitoring the spectral fingerprint of the optical emission signal to detect the etching end point. The method comprises the further insertion of an inert gas in the plasma to obtain an increase in the intensity of the optical emission signal.

Abstract: A process manufactures power MOS lateral transistors together with CMOS devices on a semiconductor substrate. The process forms a lateral MOS transistor having a gate electrode on the semiconductor region, a source comprising a first highly doped portion aligned with the gate electrode and a drain comprising a lightly doped portion aligned with the gate electrode and a second highly doped portion included in the lightly doped portion. The process forms on the lightly doped portion, a protective layer of a first material; forms on the lateral MOS transistor, a dielectric layer of a second material selectively etchable with respect to the first material; forms, in the dielectric layer first, second, and third openings; and fills the openings with a conductive layer that forms drain and source contacts electrically connected to the first and second highly doped portions, and one electrical shield substantially aligned with the protective layer.

Abstract: A power amplifier comprising at least a load element and at least an active element inserted, in series to each other, between a first and a second voltage reference is described. Advantageously, according to an embodiment of the invention, the load element comprises a DMOS transistor.

Abstract: A hybrid architecture for realizing a random numbers generator comprising a digital circuitry portion able to provide for a random bytes sequence as well as an analog circuitry portion able to provide a seed of the true random type is described.

Abstract: The invention relates to a voltage regulation system for multiword programming in non volatile memories, for example of the Flash type, with low circuit area occupation, wherein memories comprise at least a memory cell matrix organized in cell rows and columns and with corresponding circuits responsible for addressing, decoding, reading, writing and erasing the memory cell content. The memory cells have drain terminals connected to matrix columns and are biased in the programming step with a predetermined voltage value by means of program load circuits associated to each matrix column. In parallel with each program load circuit, a conduction-to-ground path is enabled by a controlled active element.

Abstract: Fuel cells are formed in a single layer of conductive monocrystalline silicon including a succession of electrically isolated conductive silicon bodies separated by narrow parallel trenches etched through the whole thickness of the silicon layer. Semicells in a back-to-back configuration are formed over etch surfaces of the separation trenches. Each semicell formed on the etch surface of one of the silicon bodies forming an elementary cell in cooperation with an opposite semicell formed on the etch surface of the next silicon body of the succession, is separated by an ion exchange membrane resin filling the separation trench between the opposite semicells forming a solid electrolyte of the elementary cell. Each semicell includes a porous conductive silicon region permeable to fluids, extending for a certain depth from the etch surface of the silicon body, at least partially coated by a non passivable metallic material.

Abstract: A control voltage for a synchronous rectifying transistor is generated with the desired anticipation time. The anticipation time is continuously controlled with a closed-loop technique by comparing it with the duration of a reference pulse. The resulting error signal is processed and provides the necessary correction to the MOSFET gate signal to equalize the actual anticipation time to the duration of the reference pulse.

Abstract: A multi-processing system-on-chip including a cluster of processors having respective CPUs is operated by: defining a master CPU within the respective CPUs to coordinate operation of said multi-processing system, running on the CPU a cluster manager agent. The cluster manager agent is adapted to dynamically migrate software processes between the CPUs of said plurality and change power settings therein.

Abstract: A cell array is formed by a plurality of cells each including a selection bipolar transistor and a storage component. The cell array is formed in a body including a common collector region of P type; a plurality of base regions of N type, overlying the common collector region; a plurality of emitter regions of P type formed in the base regions; and a plurality of base contact regions of N type and a higher doping level than the base regions, formed in the base regions, wherein each base region is shared by at least two adjacent bipolar transistors.

Abstract: A sense amplifier is provided that includes a measure branch receiving an input current to be detected, a reference branch receiving a reference current, and an equalizing circuit including a comparator. The equalizing circuit selectively equalizes a measure node of the measure branch with a reference node of the reference branch, and the comparator compares a voltage at the measure node of the measure branch with a voltage at the reference node of the reference branch. The equalizing circuit is such that, when activated, equalization of the measure node with the reference node is virtual and substantially does not involve a flow of current between the measure node and the reference node of the reference branch. The sense amplifier is particularly suited for reading memory cells of a semiconductor memory. Also provided is a method for sensing an input current.

Abstract: A non-volatile electronic memory device may be monolithically integrated on a semiconductor and be of the Flash EEPROM type having a NAND architecture and including at least one memory matrix organized in rows and columns of memory cells. Advantageously, the matrix may include at least one portion having a different data storage capacity and a different access speed than another portion.

Abstract: A method for depositing a chalcogenide layer in a phase change memory, whereby a chalcogenide layer is deposited by physical vapor deposition in a deposition chamber, having a collimator. The collimator is formed by a holed disk arranged in a deposition area delimited by the chamber walls and the chamber cover. The target is biased by a pulsed voltage to avoid charging and arching. The method is used to manufacture a phase change memory cell, whereby a resistive heater element is formed in a dielectric layer, a mold layer is formed over the dielectric layer; an aperture is formed in the mold layer over the resistive heater element; a chalcogenide layer is conformally deposited in the aperture to define a phase change portion; and a select element is formed in electrical contact with the phase change portion.