Abstract: The described converter comprises switched-capacitor quantization means for receiving an analog quantity to be converted, a register for a digital quantity corresponding to the analog quantity, a timing pulse generator and logic means capable of responding to a conversion request signal by activating the quantization means in such a way that they will carry out predetermined operations timed by the timing pulses and load in the register the digital quantity to be furnished as output. With a view to saving electric energy during the conversion and reducing the noise induced by the generator, the generator comprises means for modifying the duration and/or the frequency of the timing pulses in response to regulation signals emitted by the logic means.

Abstract: A bidirectional synchronous interface for the reception of a first flow of digital data with a first coding from a communication channel, and for the transmission on the communication channel of a second flow of digital data with the first coding in synchrony with a local timing signal. The interface includes a synchronization circuit for synchronizing the interface with the first flow of digital data that includes a first circuit fed by the local timing signal to generate, starting from the local timing signal, a plurality of repetition timing signals delayed from one another by fractions of a period, and a second circuit means fed by the first flow of digital data and by the plurality of repetition timing signals suitable for determining, from the plurality of repetition timing signals, a pre-selected repetition timing signal substantially in synchrony with the first flow of digital data.

Abstract: A stop and release circuit of a sync signal, to temporarily suspend or interrupt the sync signal, the input sync signal having a plurality of leading edges and a plurality of trailing edges, the circuit including a first divider that receives the input sync signal and supplies a first signal made up of the sync signal divided by two starting from a leading edge, a second divider that receives the inverse input sync signal and supplies a second signal made up of the sync signal divided by two starting from a trailing edge, an exclusive OR circuit that receives the first signal and the second signal and that supplies an output sync signal, a stop circuit for the first divider and the second divider, and an asynchronous command signal generated by the stop circuit for the temporary interruption of the output sync signal.

Abstract: A system controls the speed of a Voice Coil Motor (VCM) in order to perform the ramp loading of hard disk heads with low noise. This system includes a generator for generating a discontinuous PWM drive signal to a power stage. A sampling block is clocked by a synchronization signal issued from the generator and receives as an input a signal related to the electromotive force (Bemf) provided by the VCM motor. An adder node placed at the sampling block output receives a signal related to a reference electromotive force (Bemf_ref). A filtering block placed downstream of the adder node generates a power supply voltage signal to the power stage. The control system further includes a control block having at least one voltage divider and controlled switches. The control block is input the signal issued from the filtering block and control signals from the generator block to selectively operate the controlled switches and set the value of the power-on signal of the power stage.

Abstract: An electric circuit includes a circuit path from a first reference voltage to a second reference voltage lower than the first reference voltage. The patha current generator, a capacitor, a first switching element suitable for connecting or disconnecting the capacitor with respect to the current generator. The first switching element has a triggering value and the electric circuit includes a second switching element placed in parallel to the capacitor and control elements suitable for acting on the first and second switching elements for controlling the charging and discharging of the capacitor. The control elements comprise a comparator operable during the charging of the capacitor and suitable for acting on the first switching element for blocking the charging of the capacitor when the voltage value at its terminals reaches a threshold voltage value. The threshold voltage value is lower than the triggering voltage of the first switching element and higher than the second reference voltage.

Abstract: A memory device includes a plurality of memory cells each one for storing a value, at least one reference cell, biasing means for biasing a set of selected memory cells and the at least one reference cell with a biasing voltage having a substantially monotone time pattern, means for detecting the reaching of a threshold value by a current of each selected memory cell and of each reference cell, and means for determining the value stored in each selected memory cell according to a temporal relation of the reaching of the threshold value by the currents of the selected memory cell and of the at least one reference cell. The biasing means includes means for applying a controlled biasing current to the selected memory cells and to the at least one reference cell.

Abstract: A protection method may prevent a load-mismatch-induced failure in solid-state power amplifiers. In an RF power amplifier, the load voltage standing-wave ratio results in very high voltage peaks at the collector of the final stage and may eventually lead to permanent failure of the power transistor due to avalanche breakdown. The method avoids breakdown by attenuating the input power to the final stage during overvoltage conditions, thus limiting the output collector swing. This is accomplished by a feedback control system, which detects the peak voltage at the output collector node and clamps its value to a given threshold by varying the circuit gain. Indeed, the control loop is unlocked in the nominal condition and it acts when an output mismatching condition is detected. A control circuit also allows a supply-independent collector-clamping threshold to be accurately set.

Abstract: The circuit distributes a test signal applied to a pad of an electronic device that is enabled during test phases of the device and disabled during normal functioning. The circuit includes a “master” buffer, one or more “slave” buffers, one for each replicated pad, and an interconnection bus of the “master” and “slave” buffers. During a test phase, the “master” buffer replicates on the interconnection bus the test signal fed to a pad of the device, while the “slave” buffers convey to the various replica pads of the feed pad the signal present on the interconnection bus. During the normal operation of the device, the circuit remains disabled.

Abstract: Manufacturing of a wafer made of semiconductor material on insulator including the steps of: providing a composite wafer having a substrate, an insulating layer and an active layer of semiconductor material, arranged on top of one another; forming at least one deep trench within the active layer of the composite wafer, having at least one side wall; and filling at least partially the deep trench with insulating material. Prior to the filling step, the step is carried out of coating the side wall of the deep trench with a gettering layer, having the function of segregating the impurities within the active layer.

Abstract: A power electronic device is integrated on a semiconductor substrate of a first type of conductivity. The device includes a plurality of elemental units, and each elemental unit includes a body region of a second type of conductivity which is realized on a semiconductor layer of the first type of conductivity formed on the semiconductor substrate, and a column region of the first type of conductivity which is realized in said semiconductor layer below the body region. The semiconductor layer includes multiple semiconductor layers which overlap each other. The resistivity of each layer is different from that of the other layers. The column region includes a plurality of doped sub-regions, each realized in one of the semiconductor layers. The amount of charge of each doped sub-region balances the amount of charge of the corresponding semiconductor layer in which each doped sub-region is realized.

Abstract: A circuit apparatus with LED diodes includes a plurality of circuit branches in which each circuit branch comprises at least one LED diode. The apparatus comprises a device for the supply of said plurality of circuit branches and each circuit branch is connected singularly to the supply device. The supply device comprises a controller suitable for commanding the supply of each circuit branch of the plurality of circuit branches independently from the other circuit branches of the plurality.

Abstract: A random-bit sequence generator includes a biasing circuit, a source of a noisy voltage signal biased by the biasing circuit, an amplification stage generating an amplified signal representative of the sole non-zero-frequency (AC) component of the noisy voltage signal and an output stage electrically in cascade to the amplification stage that generates a random bit sequence in function of the amplified signal. The generator also filters the undesired low-frequency disturbance components because the amplification stage comprises an input low-pass filter that feeds the zero- (DC) component of the noisy voltage signal to one of the inputs of a differential amplifier, to another input of which is fed the non-filtered noisy voltage signal.

Abstract: A process for realizing an estimate of global motion based on a sequence of subsequent video images, such as those received via an optical mouse (M) for the purposes of detecting its movement.

Abstract: A digital-to-analog converter includes a first section (MSB) that converts the more significant bits of a digital code into a first voltage (Vin) of a multiplicity of discrete voltages that are integral multiples of a predetermined first voltage step (?V1). A second section (LSB) of the converter converts the less significant bits of the digital code into a current. The current is transformed into a second voltage of a multiplicity of discrete voltages that are integral multiples of a second voltage step (?V2) equal to ½L of the product of the first voltage step (?V1) multiplied by a predetermined coefficient, where L is the number of the less significant bits of the digital code to be converted. A summer generates an output voltage (Vout) that is the sum of the second voltage and the product of the first voltage multiplied by the predetermined coefficient. With a view to obtaining a low consumption, the summer has a resistive feedback circuit including a voltage divider (R3, R4).

Abstract: The present invention refers to a cascode amplifier suitable for amplifying a voltage signal present on the input terminal. The amplifier comprises at least one first transistor comprising a non-drivable input terminal that coincides with the input terminal of the amplifier, a non-drivable output terminal and a drivable terminal connected to a first polarization voltage. The amplifier comprises in addition at least one second transistor comprising a non-drivable input terminal in common with the output terminal of the first transistor, an output terminal non-drivable connected to a second polarization voltage and a drivable terminal.

Abstract: A manufacturing process of a semiconductor piezoresistive accelerometer includes the steps of: providing a wafer of semiconductor material; providing a membrane in the wafer over a cavity; rigidly coupling an inertial mass to the membrane; and providing, in the wafer, piezoresistive transduction elements, that are sensitive to strains of the membrane and generate corresponding electrical signals. The step of coupling is carried out by forming the inertial mass on top of a surface of the membrane opposite to the cavity. The accelerometer is advantageously used in a device for monitoring the pressure of a tire of a vehicle.

Abstract: A system for correcting errors in read-only memory devices by means of memory patches, wherein patch data is used as read data in the place of erroneous data stored at a given location in the memory. The system includes a processing core, such as an ARM processor, adapted to perform opcode accesses as well as data accesses to memory addresses being patched. The processing core is configured for providing different patch-data for correcting errors depending on whether it is performing a code access or a data access to an address being patched.

Abstract: A device includes at least two circuit branches, each of said at least two circuit branches comprising at least one LED diode. The device comprises a supply circuit that provides an electric supply of said at least two circuit branches and includes a variable resistance. The device comprises a controller coupled to said at least two circuit branches and suitable for varying said resistance in reply to a variation of the current that flows in one of said at least two circuit branches to vary the electric supply of said at least two circuit branches.

Abstract: A method for manufacturing electrically non-active structures for an electronic circuit integrated on a semiconductor substrate is provided, with the electronic circuit including first and second electrically active structures. The method includes inserting the electrically non-active structures in the electronic circuit to make uniform a surface above the semiconductor substrate. The inserting includes identifying, among the electrically non-active structures, a first group of electrically non-active structures to be adjacent the first and second electrically active structures, and identifying, among the electrically non-active structures, a second group of electrically non-active structures not adjacent to the first and second electrically active structures. The method further includes defining, on the semiconductor substrate, the first and second groups of electrically non-active structures through different photolithographic steps.

Abstract: A system for providing controlled access to a memory area storing code and data, includes a processor cooperating with the memory area. The processor is configured for marking the instructions processed with a field describing the origin of the code being executed, and enabling data access in the memory area only from authorized code. Typically, the processor includes a pipeline emulation block, and the controlled access to said memory area is implemented via the pipeline emulation block. The processor may be a RISC processor, such as an ARM processor, configured for associating with the instructions currently in the pipeline a bit marking if the instruction in question has been executed from an authorized memory area or not.