Patents Assigned to STMicroelectronics S.r.l.
  • Method and circuit for filtering glitches
    Publication number: 20060186927
    Abstract: A circuit for filtering glitches that corrupt a digital input signal includes an enable path input with the digital signal and a reset signal. The enable path generates a corresponding active output signal when the reset signal is null and the digital signal assumes a logic active value, or a null output signal when the reset signal is asserted. The circuit also includes a delay line producing an internal signal as delayed replica of the output signal. The circuit further includes a disable path enabled or disabled by the internal signal, which receives the digital signal and, when enabled, asserts the reset signal when the digital signal becomes null.
    Type: Application
    Filed: December 9, 2005
    Publication date: August 24, 2006
    Applicant: STMicroelectronics S.r.l.
    Inventors: Pietro Cusmano, Floriano Montemurro, Roberto Ruggirello
  • Voltage regulator
    Publication number: 20060186865
    Abstract: A voltage regulator may include an output stage controlled by a control voltage determined as a function of the difference between a reference voltage and a signal representing an output voltage of the regulator generating the output voltage on an output node of the regulator. An auxiliary stage may be connected in parallel to the output stage and cooperate therewith in supplying a load connected to the regulator. A sensing resistance may be connected in series with the output stage, and an voltage drop amplifier may be connected to the sensing resistance to generate a second control voltage of the auxiliary stage.
    Type: Application
    Filed: February 8, 2006
    Publication date: August 24, 2006
    Applicant: STMicroelectronics S.r.l.
    Inventors: Michele Placa, Ignazio Martines, Michelangelo Pisasale
  • Thermal protection device for an integrated power MOS
    Publication number: 20060186818
    Abstract: A thermal protection device is for an integrated power MOSFET transistor including an interdigitated array of source regions and drain regions defined in a well region of the monocrystalline silicon substrate, and gate structures overhanging channel regions defined between adjacent source and drain regions. The thermal protection device may include a temperature sensor and a comparator for generating an over temperature flag signal usable for turning off the overheated power transistor.
    Type: Application
    Filed: February 9, 2006
    Publication date: August 24, 2006
    Applicant: STMicroelectronics S.r.l.
    Inventors: Edoardo Botti, Fabio Cagnetti
  • Single-stage and modular multi-stage clock-booster
    Patent number: 7095268
    Abstract: A single-stage clock booster produces a boosted clock voltage on an output node that is a multiple of a supply voltage. The single-stage clock booster includes a pump capacitor having a first terminal being driven by a first control phase signal. A first switch is controlled by the boosted clock voltage for connecting a second terminal of the pump capacitor to the supply voltage during a charge phase. A second switch connects the second terminal of the pump capacitor to the output node during a boosted clock voltage output phase. A switching circuit alternately connects a control node of the second switch to the supply voltage and to the first terminal of the pump capacitor. The switching circuit is driven by a second control phase signal. A third switch is controlled by a third control phase signal for connecting the output node to a reference voltage during the charge phase.
    Type: Grant
    Filed: January 11, 2005
    Date of Patent: August 22, 2006
    Assignee: STMicroelectronics S.r.l.
    Inventors: Domenico Pappalardo, Carmelo Ucciardello, Gaetano Palumbo, Paolo Scalisi
  • Emitter switching configuration and corresponding integrated structure
    Patent number: 7095084
    Abstract: An emitter switching configuration having at least one bipolar transistor and a MOS transistor having a common conduction terminal and a Zener diode inserted between a control terminal of the bipolar transistor and the common conduction terminal. A monolithic structure is also provided that is effective in implementing the emitter switching configuration.
    Type: Grant
    Filed: January 30, 2004
    Date of Patent: August 22, 2006
    Assignee: STMicroelectronics S.r.l.
    Inventor: Cesare Ronsisvalle
  • AC differential amplifier with reduced low corner frequency
    Patent number: 7095279
    Abstract: An AC differential amplifier includes a pair of identical differential transconductance stages. Each transconductance stage includes a pair of inputs and a pair of outputs. The pairs of output of the transconductance stages are connected in common, and form a pair of output nodes of the AC differential amplifier. The pair of output nodes is also connected to a supply line through respective load resistors. One input of one transconductance stage is coupled through a capacitive device to an input of the other transconductance stage. The other inputs of the transconductance stages form the input terminals of the AC differential amplifier.
    Type: Grant
    Filed: August 26, 2004
    Date of Patent: August 22, 2006
    Assignee: STMicroelectronics S.r.l.
    Inventor: Giacomino Bollati
  • Circuit for generating an internal enabling signal for an output buffer of a memory
    Publication number: 20060181311
    Abstract: A circuit is for generating an internal enabling signal for the output buffer of a memory as a function of external commands for enabling the memory and for outputting data. The circuit may be input with the external command for enabling the memory and with internally generated flags signaling when the memory is being read and when a read operation of data from the memory ends. The circuit may generate a first intermediate signal having a null logic value when the memory is enabled and the read operation of data from the memory ends. The circuit may further generate the internal enabling signal as a logic NOR between the first intermediate signal and a logic OR between the external command enabling the memory and the external command for outputting data.
    Type: Application
    Filed: January 20, 2006
    Publication date: August 17, 2006
    Applicant: STMicroelectronics S.r.l.
    Inventors: Antonino La Malfa, Marco Messina
  • Process for manufacturing a schottky contact on a semiconductor substrate
    Publication number: 20060183267
    Abstract: A process realizes a Schottky contact on an epitaxial layer of a semiconductor substrate. The process includes depositing a conductive metallic layer on a surface of the epitaxial layer, with achievement of a interface region of conductive metallic layer/semiconductor. The process further comprises a ionic irradiation step directed towards the surface of the epitaxial layer for forming a modified intermediate layer of at least one surface portion of the epitaxial layer for making the electric behavior of the interface region substantially dependant on the contact between the conductive metallic layer and the obtained modified intermediate layer.
    Type: Application
    Filed: September 27, 2005
    Publication date: August 17, 2006
    Applicant: STMicroelectronics S.r.l.
    Inventors: Fabrizio Roccaforte, Vito Raineri, Francesco La Via, Mario Saggio
  • Process for manufacturing a memory with local electrical contact between the source line and the well
    Publication number: 20060180850
    Abstract: A process for manufacturing a memory having a plurality of memory cells includes the steps of forming a well (having a first type of conductivity) within a wafer of semiconductor material, defining active regions within the well extending in a first direction, forming memory cells within the active regions (each memory cell having a source region with a second type of conductivity opposite to the first type of conductivity), and forming lines of electrical contact which electrically contact source regions aligned in a second direction. The step of forming lines of electrical contact includes forming an electrical contact between the source regions and portions of the well adjacent thereto in the second direction.
    Type: Application
    Filed: January 12, 2006
    Publication date: August 17, 2006
    Applicant: STMicroelectronics S.r.l.
    Inventors: Daniela Brazzelli, Giorgio Servalli, Davide Erbetta, Maria Marangon
  • Method for manufacturing non-volatile memory devices integrated in a semiconductor substrate
    Publication number: 20060183281
    Abstract: A method manufactures non-volatile memory devices integrated on a semiconductor substrate and including a matrix of non-volatile memory cells and associated circuitry. The manufacturing method includes: forming a plurality of electrodes of the matrix memory cells, each electrode including a first dielectric layer, a first conductive layer, a second dielectric layer and a second conductive layer; and forming a plurality of electrodes of transistors of the circuitry each including a first dielectric layer and a first conductive layer. The method also includes forming first coating spacers on the side walls of the gate electrodes of the memory cell and second coating spacers on the side walls of the gate electrodes of the circuitry, the second spacers being wider than the first spacers.
    Type: Application
    Filed: December 27, 2005
    Publication date: August 17, 2006
    Applicant: STMicroelectronics S.r.l.
    Inventors: Carlo Cremonesi, Alessandro Grossi, Giulio Albini
  • MOS power device with high integration density and manufacturing process thereof
    Patent number: 7091558
    Abstract: A MOS power device having: a body; gate regions on top of the body and delimiting therebetween a window; a body region, extending in the body underneath the window; a source region, extending inside the body region throughout the width of the window; body contact regions, extending through the source region up to the body region; source contact regions, extending inside the source region, at the sides of the body contact regions; a dielectric region on top of the source region; openings traversing the dielectric region on top of the body and source contact regions; and a metal region extending above the dielectric region and through the first and second openings.
    Type: Grant
    Filed: January 23, 2004
    Date of Patent: August 15, 2006
    Assignee: STMicroelectronics S.r.l.
    Inventors: Ferruccio Frisina, Giuseppe Ferla, Angelo Magri′, Dario Salinas
  • Phase-change memory device with biasing of deselected bit lines
    Patent number: 7092277
    Abstract: A memory device is proposed.
    Type: Grant
    Filed: August 25, 2004
    Date of Patent: August 15, 2006
    Assignee: STMicroelectronics, S.r.l.
    Inventors: Ferdinando Bedeschi, Claudio Resta
  • Junction electronic component and an integrated power device incorporating said component
    Patent number: 7091559
    Abstract: A junction device including at least a first type semiconductor region and a second type semiconductor region a, which are arranged contiguous to one another and have a first and, respectively, a second type of conductivity, which are opposite to one another, and a first and a second biasing region (; the device is moreover provided with a resistive region, which has the first type of conductivity and extends from the first type semiconductor region and is contiguous to the second type semiconductor region so as to form a resistive path between the first and the second biasing regions.
    Type: Grant
    Filed: April 1, 2004
    Date of Patent: August 15, 2006
    Assignee: STMicroelectronics S.r.l.
    Inventors: Leonardo Fragapane, Antonino Alessandria
  • MOS device and a process for manufacturing MOS devices using a dual-polysilicon layer technology with side contact
    Patent number: 7091570
    Abstract: A MOS device has: a semiconductor body defining a surface; a stack on top of the semiconductor body; and a passivation layer on top of the semiconductor body and covering the stack. The stack is formed by a first polysilicon region and by a second polysilicon region arranged on top of one another and separated by an intermediate dielectric region. An electrical connection region extends through the passivation layer as far as the surface of the semiconductor body laterally with respect to, and in contact with, the first and the second polysilicon regions so as to contact them electrically.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: August 15, 2006
    Assignee: STMicroelectronics S.r.l.
    Inventors: Carlo Caimi, Paolo Caprara, Valentina Tessa Contin, Davide Merlani
  • Water-based electrolyte gel for dye-sensitized solar cells and manufacturing methods
    Publication number: 20060174938
    Abstract: A dye-sensitized solar cell is provided having an organic compound to absorb solar radiation and donate electrons, a semiconductor to transport electrons, and a hole transporting material formed of a water-based electrolyte gel that includes a polymeric compound and a electrolyte solution. Preparation of the water based gel includes gelling a hydrophilic polymer that is present at least in a concentration, depending on molecular weight and/or degree of hydrolyses and/or degree of polymerization, sufficient to form the gel from the aqueous solution.
    Type: Application
    Filed: October 25, 2005
    Publication date: August 10, 2006
    Applicants: STMicroelectronics S.r.l., Università degli Studi di Napoli Federico II
    Inventors: Vincenza Di Palma, Angela Cimmino, Rossana Scaldaferri, Cosimo Carfagna, Antonella De Maria, Valeria Casuscelli
  • Removable data storage device and related assembling method
    Publication number: 20060176673
    Abstract: A removable storage device includes a substrate whereon a plurality of components are arranged. Advantageously, the removable storage device comprises a casing of the package type suitable to completely cover these components and to form, together with the substrate, an external coating of the removable storage device. Moreover, a method is described for assembling at least one removable storage device thus realized.
    Type: Application
    Filed: January 31, 2006
    Publication date: August 10, 2006
    Applicant: STMicroelectronics S.r.l
    Inventors: Marco Roveda, Davide Villa, Romina Zonca, Stefano Ghezzi, Stefano Saltutti, Luigi Costanzo
  • Nonvolatile switch, in particular for high-density nonvolatile programmable-logic devices
    Patent number: 7088135
    Abstract: A nonvolatile switch has: an input terminal; an output terminal; a selection terminal; a first and a second biasing terminal; a memory element of flash type, having a first conduction region connected to the first biasing terminal and a second conduction region connected to the second biasing terminal; a pass transistor, having a first conduction region connected to the input terminal and a second conduction region connected to the output terminal; and a common floating gate region and a common control gate region, which are capacitively coupled together. The memory element and the pass transistor share the common-gate regions, and the common control gate region is connected to the selection terminal.
    Type: Grant
    Filed: January 20, 2004
    Date of Patent: August 8, 2006
    Assignee: STMicroelectronics S.r.l.
    Inventors: Chantal Auricchio, Michele Borgatti, Pier Luigi Rolandi
  • Low-noise, high-linearity analog multiplier
    Patent number: 7088169
    Abstract: An analog multiplier for multiplying a first analog voltage signal at a first frequency by a second analog voltage signal at a second frequency, comprising a first stage for converting the first analog voltage signal into a first and a second current signals, and a second stage comprising a first and a second cross-coupled current-switching pairs, driven by the second voltage signal, the first and second current-switching pairs having respective current inputs for receiving the first and the second current signals, respectively. Parasitic capacitances are inherently associated with each current input of the current-switching pairs. A compensation circuit is coupled to the current inputs of the current-switching pairs for compensating the parasitic capacitances.
    Type: Grant
    Filed: February 18, 2004
    Date of Patent: August 8, 2006
    Assignee: Stmicroelectronics, S.R.L.
    Inventors: Simone Erba, Giampiero Montagna, Mario Valla
  • Programming method for a multilevel memory cell
    Patent number: 7088614
    Abstract: A programming method of a multilevel memory cell is able to store a plurality of bits in a plurality of levels. The method includes writing a logic value in the multilevel memory cell by setting one of the programming levels thereof, these levels being included in the plurality of levels, with respect to a reference level according to the symbol to be written and to a previous programming level. The writing step is repeated until a highest possible value for the levels is reached. A multilevel memory device includes a plurality of multilevel memory cells organized into sectors, split into a plurality of data units whereon a programming operation is performed in parallel.
    Type: Grant
    Filed: December 26, 2002
    Date of Patent: August 8, 2006
    Assignee: STMicroelectronics S.r.l.
    Inventors: Guido De Sandre, Marco Poles, David Iezzi, Marco Pasotti
  • Memory device
    Publication number: 20060171222
    Abstract: A memory device an array of memory cells, the array including word lines and bit lines. The memory device also includes managing logic for managing array reading operations that are carried out by executing a step of precharging the bit lines and a step of turning on the word lines. The managing logic includes a control block for generating a first enable signal of the precharge step and a second enable signal of the turning on step such that, within the same reading operation, the precharge and turning on steps are partially concurrent.
    Type: Application
    Filed: December 27, 2005
    Publication date: August 3, 2006
    Applicant: STMicroelectronics S.r.l.
    Inventors: Gianluca Blasi, Barbara Vese