Abstract: A parallel sense amplifier includes a measuring branch for receiving an input current to be measured, a plurality of reference branches each one for receiving a reference current, and a plurality of comparators each one for comparing a voltage at a measuring node along the measuring branch with a voltage at a reference node along a corresponding reference branch; the amplifier further includes a multiple current mirror for mirroring the input current into each reference branch.

Abstract: A lead-frame for semiconductor devices having a mold with at least one air vent for the resin to seep out of during its injecting into the mold, the air vent being positioned between the upper and lower surface of the frame, wherein the frame provides a through hole positioned at the outlet of the air vent so that, when the resin has solidified, it forms a flash which is in coherence with the surface of the frame.

Abstract: Protecting the devices of a charge pump includes the connection of a high-voltage transistor between the output node of the charge pump and the load being supplied, and in controlling this transistor with a fraction of the output voltage of the charge pump. This control is accomplished by connecting the control node of the high-voltage transistor to a node of connection between two stages of the multi-stage charge pump onto which a fraction of the controlled output voltage of the multi-stage charge pump is produced. The high-voltage output transistor protects the low voltage devices of the multi-stage charge pump, by preventing the controlled output voltage from undergoing excessively abrupt variations, that could damage the transistors of the last stage of the charge pump.

Abstract: The method is for manufacturing electronic memory devices on a semiconductor substrate including a non-volatile memory matrix and associated circuitry. The method includes forming a first insulation layer, a conductive layer and a second insulation layer. A resist mask is formed corresponding with the memory matrix to define a predetermined geometry in the second insulation layer. The exposed portions of the second insulation layer are isotropically etched. Also, a conformal protective layer is formed and removed via a second highly selective etching step to form portions of the conformal protective layer on side walls of the resist mask and of the insulation layer. A third isotropic etching step removes the insulation layers left exposed by the resist mask and by the portions of the protective layer. The portions of the conformal protective layer and of the resist mask are then removed.

Abstract: An integrated device comprising a MOS transistor and a Schottky diode which are formed on a semiconductor substrate of a first conductivity type is shown. The device comprises a plurality of body region stripes of a second conductivity type which are adjacent and parallel to each other, a first metal layer placed over said substrate and a second metal layer placed under said substrate. The device comprises a plurality of elementary structures parallel to each other each one of which comprises first zones provided with a silicon oxide layer placed over a portion of the substrate which is comprised between two adjacent body region stripes, a polysilicon layer superimposed to the silicon oxide layer, a dielectric layer placed over and around the polysilicon layer. Some body region stripes comprise source regions of the first conductivity type which are placed adjacent to the first zones of the elementary structures to form elementary cells of said MOS transistor.

Abstract: A method for locating in an array of memory cells a set of cells having a stand-by current that exceeds a certain value based on their programming state. The method includes selecting all the cells of the array of memory cells as a set of cells to be tested, and dividing the set of cells to be tested into subsets of cells, and repeatedly sensing a stand-by current absorbed by the array of memory cells after having changed the programming state of the subsets of cells. The sensed stand-by currents are compared and a subset of cells having a stand-by current exceeding the certain value are identified as a function of the comparison. The identified subset of cells is selected as a new set of cells to be tested, and the method is repeated. Otherwise, the testing stops with the just tested subset of cells having a stand-by current exceeding the certain value.

Abstract: For manufacturing an SOI substrate, the following steps are carried out: providing a wafer of semiconductor material; forming, inside the wafer, a plurality of passages forming a labyrinthine cavity and laterally delimiting a plurality of pillars of semiconductor material; and oxidizing the pillars of semiconductor material to form a buried insulating layer. For forming the labyrinthine cavity, a trench is first formed in a substrate; an epitaxial layer is grown, which closes the trench at the top; the wafer is annealed so as to deform the pillars and cause them to assume a minimum-energy handlebar-like shape, and a peripheral portion of the wafer is removed to reach the labyrinthine cavity, and side inlet openings are formed in the labyrinthine cavity. Oxidation is performed by feeding an oxidizing fluid through the side inlet openings.

Abstract: A nonvolatile memory with a memory array arranged in rows and columns of memory cells in NOR configuration, the memory cells arranged on a same column being connected to one of a plurality of bit lines and a column decoder. The column decoder comprises a plurality of selection stages, each of which is connected to respective bit lines and receives first bit line addressing signals. The selection stages comprise word programming selectors controlled by the first bit line addressing signals and supplying a programming voltage to only one of the bit lines of each selection stage. Each selection stage moreover comprises a string programming selection circuit controlled by second bit line addressing signals thereby simultaneously supplying the programming voltage to a plurality of the bit lines of each selection stage.

Abstract: The control circuit is for a current sharing bus integrated in signal regulator modules, particularly voltage regulator modules (VRM), the circuit being of the Average Program (AP) type. The circuit includes a voltage regulator module, including an operational transconductance amplifier, a first current generator, connected to a first input terminal of the operational transconductance amplifier, a second current generator connected to a second input of the operational transconductance amplifier. The operational transconductance amplifier is directly driven by currents Ii generated by the first current generator and second current generator.

Abstract: A phase change memory device includes a plurality of phase-change memory cells, arranged in rows and columns, phase-change memory cells arranged on the same column being connected to a same bit line; a plurality of first selectors, each coupled to a respective phase-change memory cell; an addressing circuit for selectively addressing at least one of the bit lines, one of the first selectors, and the phase-change memory cell connected to the addressed bit line and to the addressed first selector; and a regulated voltage supply circuit, selectively connectable to the addressed bit line, for supplying a bit line voltage. The bit line voltage is correlated to a first control voltage on the addressed first selector, coupled to the addressed phase-change memory cell.

Abstract: A quantum gate performs the superposition operation of a Grover's or of a Deutsch-Jozsa's quantum algorithm in a very fast manner. This is done by performing all multiplications by using logic gates that immediately outputs the result. The superposition operation includes performing the Hadamard rotation over an input set of vectors for producing a set of rotated vectors, and calculating the tensor product of all the rotated vectors for outputting a linear superposition set of vectors. The tensor product of all the rotated vectors is carried out by the logic gates.

Abstract: A method manufactures a single electron transistor device by electro-migration of nanocluster wherein said nanoclusters are metallically passivated and forced to assembly over a lithographic patterned substrate under control of a non homogeneous electric field at room temperature. A controlled migration and the desired location of the metallic passivated nanoclusters are based on a dielectrophoretic process.

Abstract: A vertical-conduction and planar-structure MOS device having a double thickness gate oxide includes a semiconductor substrate including spaced apart active areas in the semiconductor substrate and defining a JFET area therebetween. The JFET area also forms a channel between the spaced apart active areas. A gate oxide is on the semiconductor substrate and includes a first portion having a first thickness on the active areas and at a periphery of the JFET area, and a second portion having a second thickness on a central area of the JFET area. The second thickness is greater than the first thickness. The JFET area also includes an enrichment region under the second portion of the gate oxide.

Abstract: A serial interface for communicating with peripherals may include a circuit for generating pointers to addresses in sections of a memory, and a circuit for serially transferring data from or to at least one peripheral connected to the interface that is coupled to the memory based upon requisite configuration commands. The interface may further include a control register coupled to the memory and to the serial transfer circuit for controlling data to be transmitted or received. The interface does not require that an external controller provide configuration commands each time data is transmitted or received because the memory sections for storing data may be divided in distinct memory spaces. That is, each memory space may store data for a respective peripheral connected to the interface. Moreover, another memory section may be used to store all of the configuration commands of the interface required for communicating with the peripherals.

Abstract: A device and method for programming an electrically programmable memory applies at least one first programming pulse to a group of memory cells (MC1–MCk) of the memory, accesses the memory cells of the group to ascertain a programming state thereof, and applies at least one second programming pulse to those memory cells in the group whose programming state is not ascertained to correspond to a desired programming state. A voltage applied to a control electrode of the memory cells is varied between the at least one first programming pulse and the at least one second programming pulse according to a forecasted change in biasing conditions of the memory cells in the group between said at least one first and at least one second programming pulses. Undesired over-programming of the memory cells is thus avoided.

Abstract: A voltage regulator connected to a memory cell is configured by identifying at least a first and a second operation regions of the cell and associating the first and second operation regions with respective first and second operation conditions of the memory cell. An operative condition of the memory cell involved in a programming operation is detected, and at least a configuration signal of the regulator according to said detected operative condition is generated, this configuration signal taking a first and a second value associated with the first and second operation conditions.

Abstract: A process is presented for realizing buried microchannels (10) in an integrated structure (1) comprising a monocrystalline silicon substrate (2). The process forms in the substrate (2) at least one trench (4). A microchannel (10) is obtained starting from a small surface port of the trench (4) by anisotropic etching of the trench. The microchannel (10) is then completely buried in the substrate (2) by growing a microcrystalline structure to enclose the small surface port.

Abstract: A transition mode operating device for the correction of the power factor in switching power supply units includes a converter for receiving an input voltage and for providing a regulated output voltage, and a coupled control device. The converter includes a power transistor, a rectifier, and an inductor and auxiliary winding arranged between the rectifier and a power transistor. The control device includes a circuit for generating an error signal, a multiplier for receiving the error signal, and a driving circuit coupled to the multiplier to determine the on time period and the off time period of the power transistor. The control device includes circuitry coupled to the auxiliary winding of the inductor to generate a signal proportional to the input voltage during the on time of the power transistor and a signal representative of the current flowing through the power transistor.

Abstract: A method is described for manufacturing electronic semiconductor devices comprising the steps of depositing in sequence a layer of hydrophobic material and a “deep UV” photo-resist layer on a semiconductor substrate, selectively removing the “deep UV” photo-resist layer and hydrophobic material in order to expose definite portions of the semiconductor substrate and etch the exposed portions by means of an watery acid solution. This method allows semiconductor devices to be manufactured, also having very critical sizes and with a convenient resolution and control of circuit patterns formed thereon through etching with watery acid solutions.

Abstract: A resistive structure integrated in a semiconductor substrate and having a suitably doped polysilicon region that is completely surrounded by a dielectric region so that the resistive structure is isolated electrically from other components jointly integrated in the semiconductor substrate.