Abstract: A method for verifying an array cell of a memory device may include determining after each erase pulse or program pulse the threshold of a cell addressed through a selected array word-line and bit-line, by applying an identical voltage ramp to the selected array word-line and to the control gate of a reference cell, while biasing at a certain voltage deselected word-lines through distribution lines of the voltage generated by a charge pump generator. The method may further include temporarily decoupling the deselected word-lines from the distribution lines of the bias voltage for the duration of the voltage ramp.

Abstract: A gain stage control method may include providing a control current signal; generating a regulation current signal connected to the control current signal; transforming the regulation current signal into a biasing current, proportional to the regulation current signal; and biasing the gain stage by using the biasing current. The biasing current may be related to the control current signal by an exponential law.

Abstract: A process manufactures an interpoly dielectric layer for non-volatile memory cells of a semiconductor device with an interpoly dielectric layer. The process begins with forming the tunnel oxide, and hence the amorphous or polycrystalline silicon layer, using conventional techniques. After the amorphous or polycrystalline silicon layer is surface cleansed and passivated, the surface of the polycrystalline layer is nitrided directly by using radical nitrogen. This is followed by the formation of the interpoly dielectric, either as an ONO layer or a single silicon layer, by means of the CVD technique. Masking to define the floating gate may be performed immediately before or after the direct nitridation step is carried out. The equivalent electrical thickness of the interpoly dielectric, obtained by combining the nitride oxide layer and by the following dielectric, does not exceed 130 Angstroms in either the ONO layer or the single silicon layer embodiment.

Abstract: A plurality of non volatile memory cells, for example of the flash type, with low circuit area occupation, are organized in cell matrices with corresponding circuits responsible for addressing, decoding, reading, writing and erasing the memory cell content. Each of the cells has a gate terminal biased in the programming phase with a predetermined voltage value through operation of charge pump voltage regulators. A first and a second regulation stage, which are structurally independent, are responsible for the programming and soft programming phase respectively. The first stage generates a supply voltage for the second stage.

Abstract: A device for effectuating a digital estimate of a periodic electric signal is described. The device comprising a linear DAC having an output signal, a comparator that compares the output signal of the linear DAC with the periodic electric signal, and logic circuitry having in input the output signal of the comparator and a pulse clock signal. The logic circuitry provides a first digital signal in input to the linear DAC and a second digital signal representative of the estimate of the periodic electric signal.

Abstract: A device for filtering electrical signals has a number of inputs arranged spatially at a distance from one another and supplying respective pluralities of input signal samples. A number of signal processing channels, each formed by a neuro-fuzzy filter, receive a respective plurality of input signal samples and generate a respective plurality of reconstructed samples. An adder receives the pluralities of reconstructed samples and adds them up, supplying a plurality of filtered signal samples. In this way, noise components are shorted. When activated by an acoustic scenario change recognition unit, a training unit calculates the weights of the neuro-fuzzy filters, optimizing them with respect to the existing noise.

Abstract: An analog-to-digital converter (200) includes at least one stage (105) for converting an analog input signal into a digital output signal using a parallel quantizer (115) comparing the analog input signal with a plurality of threshold values in parallel. The analog-to-digital converter includes, for at least one selected stage (105), an estimating circuit (210,220) for estimating an analog correction signal indicative of the mean value of a quantization error of the selected stage, and a compensating circuit (440i) for at least partially compensating an offset error of the parallel quantizer (105) in the selected stage according to the analog correction signal. A method and computing system are also provided.

Abstract: A method for encapsulating an electronic device is provided. The electronic device includes an integrated circuit, a lead frame for supporting the integrated circuit and having peripheral leads integrally formed therewith, and a heat sink thermally coupled to the lead frame. The heat sink includes an extension extending therefrom in a direction towards a corner of the electronic device. The method includes positioning the electronic device within a mold that includes a gate therein that is adjacent to and parallel with the extension. Molten insulative material is injected through the gate and into the mold for encapsulating the integrated circuit, and at least a portion of the lead frame and the heat sink.

Abstract: MOS-gated power device including a plurality of elementary functional units, each elementary functional unit including a body region of a first conductivity type formed in a semiconductor material layer of a second conductivity type. A plurality of doped regions of a first conductivity type is formed in the semiconductor material layer, each one of the doped regions being disposed under a respective body region and being separated from other doped regions by portions of the semiconductor material layer.

Abstract: The output voltage ripple of a single stage or a multi-stage charge pump may be significantly reduced by introducing in the voltage generator a cascode connected output transistor. In operation, this output transistor may be in a conduction state and may be controlled with a voltage having a smaller ripple than the voltage output by the charge pump.

Abstract: An Integrated gyroscope includes a suspended mass; mobile actuation electrodes extending from the suspended mass; and a sensing mass connected to the actuation mass through coupling springs. The suspended mass is formed by an external part and an internal part, electrically separated by an electrical-insulation region having a closed annular shape. The electrical-insulation region is laterally completely surrounded by the external part and by the internal part. In one embodiment, the suspended mass has the shape of a closed frame delimiting an opening, the sensing mass is formed inside the opening and is connected to the internal part, and the mobile actuation electrodes are connected to the external part.

Abstract: In order to execute, as a function of a received signal (r), a procedure of channel estimation in a transmission channel with memory in a telecommunications system, there is envisaged an operation of estimation of a delay spread associated to said channel, said operation of estimation comprising calculation of a root mean square value (?rms) of delay spread by means of a step of evaluation of crossings with a threshold level of a quantity associated to a transfer function of said channel. Said step of evaluation of crossings comprises evaluating a mean number of crossings (?0) of the real and imaginary parts of said channel transfer function with a threshold level corresponding to the zero level. Example application is to OFDM telecommunications systems and in particular wireless systems according to the IEEE 802.11a WLAN standard or the Hyperlanll WLAN standard.

Abstract: An electronic memory device with a high density of non-volatile memory cells has a reduced capacitance cell-to-cell interference. The memory cells are integrated on a semiconductor substrate and are organized in a matrix of cells with word lines and bit lines connected to the cells. Each memory cell includes at least one floating gate transistor having a floating gate region projecting from the substrate, and a control gate region capacitively coupled to the floating gate region. Between the cells of opposite word lines, a lateral coating is provided that includes at least one conductive layer floating along the direction of the bit lines.

Abstract: A flash NAND electronic memory device includes non-volatile cells having a high integration density and a relative programming method. The memory device is integrated on a semiconductor substrate and includes a matrix with word lines and bit lines organized in sectors of memory cells. The memory device is between the cells of the opposite word lines belonging to at least one of the sectors of the matrix. A lateral coating along the direction of the bit lines has at least one conductive layer with a contact terminal being selectively biased or left floating during each program, read or erase operation. Each cell belongs to a sector.

Abstract: A method for determining an effective resistance of a voltage controlled DC motor having a nominal resistance includes driving the DC motor with a signal so that the DC motor has a targeted acceleration, and sensing an effective acceleration of the DC motor. The effective resistance of the DC motor is determined as a function of the nominal resistance, the targeted acceleration and the effective acceleration.

Abstract: The use of a PLL including a phase detector responsive to the phase difference between an input signal and a feedback signal and which pilots an oscillator in function of this difference, is envisaged. The PLL also includes a feedback path that is responsive to the signal generated by the oscillator and which generates said feedback signal via at least one divider with a variable division ratio. The division ratio of said divider is modulated via a sigma-delta modulator, the input of which is fed with a triangular-wave modulating signal. The preferred application is that of a spread spectrum clock generator (SSCG) for digital electronic systems.

Abstract: A step gain-variable CMOS amplifier includes an input pair of transistors, a bias current generator connected between a common source node of the input pair of transistors and a ground node, and a pair of load transistors. The pair of load transistors is connected between a supply voltage node and, respectively, to the drain nodes of the input pair of transistors. The CMOS amplifier includes a plurality of second input pairs of transistors to be connected in parallel to the input pair of transistors for increasing the effective width of the resultant transistors. Alternativelty, the CMOS amplifier includes a plurality of second load pairs of transistors to be connected in parallel to the load pair of transistors for increasing the effective width of the resultant transistors. Pairs of path selection switches may be programmably closed for connecting in parallel the selected pairs of transistors.

Abstract: A portable apparatus having an accelerometer device and a supporting element in the accelerometer device, having a first body of semiconductor material integrating a sensor element that detects movements of the first body and generates a signal correlated to the detected movement; a second body of semiconductor material that integrates a conditioning electronics and that is electrically connected to the first body; and conductive bumps that provide electrical connection of the first and second bodies to the supporting element. In particular, the conductive bumps connect the first and second bodies to the supporting element without the interposition of any packaging.

Abstract: A method controls write/erase operations in a memory device including memory blocks that are exposed to wear as a result of repeated erasures. The method includes: storing the erase counts of the memory blocks, creating a chain storing the erase counts of the memory blocks that are available for writing at a certain instant of time, and selecting for writing, out of the blocks in the memory device available for writing, the block having the lowest erase count in the chain.

Abstract: A memory device of a phase change type, wherein a memory cell has a memory element of calcogenic material switcheable between at least two phases associated with two different states of the memory cell. A write stage is connected to the memory cell and has a capacitive circuit configured to generate a discharge current having no constant portion and to cause the memory cell to change state.