Abstract: A processing system, such as typically a CPU, is used for converting a digital signal organized in pixels, such as a video signal, between a first format and a second multiple-description format. The system comprises at least one input register and at least one output register, and is configured via instructions, that can be constituted at least in part by instructions of a SIMD type, so as to: order the pixels of the signal to be converted in a set of input registers; and take selectively the pixels from the aforesaid set of input registers and place them in an orderly way in at least one output register.

Abstract: A method for controlling in an open-loop voltage mode a DC motor driven through a power amplifier includes generating a control voltage for the DC motor to be input to the power amplifier based upon a difference between an external command and a correction signal, and amplifying the control voltage for generating a replica of an output of the power amplifier. A model of the DC motor is defined based upon electrical parameters of the DC motor. The method further includes estimating current flowing in the DC motor based upon the replica of the output of the power amplifier and the model of the DC motor, and generating the correction signal proportional to the estimated current.

Abstract: A memory cell of a stacked type is formed by a MOS transistor and a ferroelectric capacitor. The MOS transistor is formed in an active region of a substrate of semiconductor material and comprises a conductive region. The ferroelectric capacitor is formed on top of the active region and comprises a first and a second electrodes separated by a ferroelectric region. A contact region connects the conductive region of the MOS transistor to the first electrode of the ferroelectric capacitor. The ferroelectric capacitor has a non-planar structure, formed by a horizontal portion and two side portions extending transversely to, and in direct electrical contact with, the horizontal portion.

Abstract: An Electric Wafer Sort (EWS) flow is implemented by expanding the functions of the micro-controller embedded in a FLASH EPROM memory device and of the integrated test structures. Test routines are executed by the onboard micro-controllers (that may be reading either from an embedded ROM or from a GLOBAL CACHE provided) internally without involving any external complex or expensive test equipment to control the test program. The device architecture is transparent from a tester point of view, with a standard interface having a set of defined commands and instructions to be interpreted by the on board microcontroller and internally executed.

Abstract: An integrated device including a first memory array having first memory cells of a nonvolatile type and a second memory array having second memory cells of a volatile type (DRAM). The first memory cells and the second memory cells are formed in a substrate of semiconductor material, and each includes a respective MOS transistor which is formed in an active region of the substrate and has a first conductive region and a respective capacitor which is formed on top of the active region and has a first electrode and a second electrode, which are separated by a dielectric region. Moreover, the first electrode of the capacitor is connected to the first conductive region of the MOS transistor. The first and the second memory cells have a structure that is substantially the same and are formed simultaneously.

Abstract: A method for estimating resistance of a DC motor for positioning read/write heads of a data storage disk is provided. The DC motor is controlled in an open-loop voltage mode through a motor controller input with a first signal for compensating positioning of the read/write heads onto the data storage disk. The first signal is generated based upon a position error signal representing a difference between a position of the read/write heads and a center of a track to be read. The method includes monitoring the first signal during a read operation of data being stored on the data storage disk, and estimating the resistance based upon spectral components of the first signal.

Abstract: A phase change memory has an array formed by a plurality of cells, each including a memory element of calcogenic material and a selection element connected in series to the memory element; a plurality of address lines connected to the cells; a write stage and a reading stage connected to the array. The write stage is formed by current generators, which supply preset currents to the selected cells so as to modify the resistance of the memory element. Reading takes place in voltage, by appropriately biasing the selected cell and comparing the current flowing therein with a reference value.

Abstract: A network, such as a network on chip, includes a plurality of levels of switches organized in a hierarchy. The connections between the switches are constituted by connections which are able to transport packets of information in opposite directions in such a way that one switch, or one process associated thereto, can send or receive packets in the framework of the network along one and the same path, constituted by an ascending stretch, in which the packet goes up the network hierarchy as far as a root switch common to the source and to the destination, and a descending stretch in which the packet goes down the network hierarchy towards the destination. A routing logic is provided, configured for defining the routing path in a non-adaptive way, selecting the ascending stretch according to the source and the descending stretch according to the destination, irrespective of the traffic of the packets.

Abstract: A voltage down converter is provided that includes a voltage regulator and voltage driver circuit branches. The voltage regulator receives a first voltage, has a regulation node providing a regulated second voltage that is lower than the first voltage, and has a control node providing a control voltage corresponding to the second voltage. One voltage driver circuit branch receives the first voltage and includes a variable-conductivity element having a control terminal coupled to the control node for controlling a current sunk by the variable-conductivity element. This one voltage driver circuit branch has a voltage supply node supplying a down-converted voltage corresponding to the second voltage. At least one additional voltage driver circuit branch receives the first voltage and is coupled to the voltage supply node.

Abstract: An oscillator is provided that includes at least one capacitor, at least one comparator, and at least one device for charging or discharging the at least one capacitor. The capacitor is coupled to the comparator. The comparator compares the voltage on the capacitor with a reference voltage, and activates the device so as to command the charging or the discharging of the capacitor. The oscillator also comprises a circuit for supplying a preset voltage to the comparator when the device commands the charging of the capacitor, so that the comparator compares the reference voltage diminished by the preset voltage with the voltage on the capacitor, or the voltage on the capacitor added to the preset voltage with the reference voltage.

Abstract: The output buffer stage includes a half-bridge output stage having a first pair of complementary drivers connected in series between a supply line and a ground node, the high impedance state or conduction state of which is determined through a pair of control phases. The buffer stage includes a pair of switches controlled by the control phases, connected in series between them and connecting the transistors of the first stage in series. Each driver is connected in series with a switch, that is quickly opened to prevent under-threshold currents from circulating when the respective driver is turned off, and that is rapidly turned off when the respective driver is turned on.

Abstract: A method for image compression of a set of image data includes performing a quantization operation on the image data. The quantization operation may include controlling a compression factor by applying a scaled quantization level obtained by multiplying a first quantization level by a gain factor. The gain factor may be updated as a function of a bit per pixel value of a compressed image. The update operation may include an iterative procedure including at least one iteration step that provides for updating a current gain factor as a function of a previous gain used for performing a previous compression step and as a function of a ratio of the bit per pixel value of the compressed image at the previous compression step to a target bit per pixel value. The method may be used in Joint Photographic Experts Group (JPEG) image processing and digital still cameras.

Abstract: A configuration terminal for integrated devices includes a first and a second portion structurally independent and connected to respective first and second terminals and it has at least one contact terminal suitable to be selectively connected to such first and second terminals. Also a method configures an integrated device that includes a plurality of address pads and respective supply pins. The method includes: realizing at least one configuration terminal having a first and a second portion structurally independent and connected to at least one contact terminal; providing the contact of such first and second portions with respective terminals; and configuring the device by a short-circuiting of the contact terminal with at least one of said terminals.

Abstract: Described is an error control method for multilevel memory cells operating with a variable number of storage levels. The method includes: receiving a first information word having k input symbols each in a first base; converting the first information word into a second base by converting the input symbols into input symbols in the second base; encoding the converted first information word into a first codeword having k+n coded symbols in the second base; and writing the first codeword into the multilevel memory cells. The encoding step may include generating a generating matrix and multiplying the first information word by the generating matrix to produce the first codeword.

Abstract: The invention relates to a circuit device for realizing a non-linear reactive elements scale network, wherein the non-linear elements of the network are pairs of inductive and capacitive components cascade connected between a pair of input terminals and a pair of output terminals. Advantageously in the invention, each component of the network is formed by cascade connecting a first and a second transconductance integrator with each other.

Abstract: A power factor correction device for switching power supplies is described, which comprises a converter (20) and a control device (100; 200; 300) coupled with said converter (20) in such a way as to obtain from a input network alternated voltage (Vin) a direct regulated voltage (Vout) at the output terminal. The converter (20) comprises a power transistor (M) and the control device (100; 200; 300) comprises an error amplifier (3) having in input at the inverting terminal a first signal (Vr) proportional to said regulated voltage (Vout) and at the non-inverting terminal a voltage reference (Vref), at least one capacitor (C) having a first terminal and a second terminal which are coupled respectively with the inverting terminal and the output terminal (31) of the error amplifier (3) and a driving circuit (4–6) of said power transistor (M) which is coupled with the second terminal of said capacitor (C).

Abstract: An injection control method for controlling a “common rail” fuel injection system in a diesel engine is described. The method includes the following steps: an initializing step for acquiring engine control parameters; and a main adjustment cycle for adjusting operational variables of the engine. The injection control method also includes an interrupting step for adjusting an injection procedure proper of the injection system by variation of all the characteristic parameters of the injection procedure. Also described is an injection control system for a diesel engine based on the above method.

Abstract: A driving circuit is for an output buffer stage, with high speed and reduced noise induced on the power supply. The driving circuit may include first and second circuit portions, each intended for the generation of a respective driving signal for a corresponding transistor of the buffer stage. Each portion may include a final stage with a complementary pair of MOS transistors inserted between two supply voltage references, and a third MOS transistor having its conduction terminals connected between one of the voltage references and an interconnection node of the complementary pair and receiving, on its control terminal, an activation pulse signal coming from a logic network incorporating at least one delay chain.

Abstract: The Flash memory device with a Low Pin Count (LPC) communication interface includes a memorization block or Flash core including a matrix of non volatile memory cells, with associated circuit portions for reading, modifying and erasing the data contained in the memory. An interface block associated with the LPC communication interface includes at least an address block, a data block and a state machine enabling the data flow from and towards the memorization block. Advantageously, the data block of the interface block is doubled in a portion provided to contain the read data and in a portion provided to contain write data. In the memorization block, respective address decoders are provided for the read and write steps of the memory matrix. The device includes an architecture of the multibank type and the logic necessary for the execution of a “Dual Operations” mode. In this way it is possible to simultaneously perform a modify operation in a memory bank and a read operation in another bank.

Abstract: A bandgap voltage generator includes an output node for providing an output voltage, a current mirror coupled between the output node and a voltage reference, and a biasing transistor coupled to the output node. A feedback line includes a feedback transistor coupled to the output node. A current generator biases the feedback transistor by injecting a current into a bias node of the feedback line. A capacitor is coupled between the bias node and the voltage reference. The feedback line includes a circuit coupled between the bias node and the feedback transistor for causing a current to flow through the feedback transistor, and for increasing a resistance of a portion of the feedback line in parallel to the capacitor.