Abstract: A digital logic system includes a reset input for receiving a reset signal, and a clock input for receiving an externally generated main clock signal. An ancillary clock generator generates an ancillary clock signal. A clock selection multiplexer has a first input for receiving the externally generated main clock signal, a second input for receiving the internally generated ancillary clock signal, and an output for providing the externally generated main clock signal or the internally generated ancillary clock signal to a functional circuit. A resettable edge-triggered shift register has a first input for receiving the externally generated main clock signal, a second input for receiving the reset signal, and an output connected to the clock selection multiplexer for deselecting the internally generated ancillary clock signal and selecting the externally generated main clock signal after detecting a certain number of edges of the main clock signal following the reset signal.

Abstract: A DC/DC converter includes a first switchcoupled to an input voltage and to a reference voltage. The first switch is suitable for driving a load connected to the output terminal of the DC/DC converter. The DC/DC converter includes an inductor having an intrinsic resistance and being connected to a terminal of the first switch, and a control circuit suitable for generating a driving signal of the first switch at a switching pulse. The control circuit has a first input terminal connected to the output terminal of the DC/DC converter. The DC/DC converter comprises a resistive element and a capacitor connected between the terminal of the first switch and the reference voltage. The control circuit has a second input terminal connected with the terminal in common of the capacitor and of the resistance.

Abstract: Digital signals, such as image/video signals are converted between a first format and a second format by using Multiple Description Coding, whereby the second format conveys multiple descriptions (D1 to D4; D1? to D4?) of the digital signals. In combination with MD coding, the signals are jointly subject to an error concealment process.

Abstract: A micro-electromechanical device includes a semiconductor body, in which at least one first microstructure and one second microstructure of reference are integrated. The first microstructure and the second microstructure are arranged in the body so as to undergo equal strains as a result of thermal expansions of the body. Furthermore, the first microstructure is provided with movable parts and fixed parts with respect to the body, while the second microstructure has a shape that is substantially symmetrical to the first microstructure but is fixed with respect to the body. By subtracting the changes in electrical characteristics of the second microstructure from those of the first, variations in electrical characteristics of the first microstructure caused by thermal expansion can be compensated for.

Abstract: A method of self-calibrating a modulator includes at least one integrator likely to incur a phase error may include reading a pulse response of the modulator, calculating a phase error parameter of the at least one integrator, and calibrating the phase error parameter. In addition, the calibration may provide a count of pulse response samples above suitable threshold values, as well as a change in the value of a capacitor associated with the integrator based upon the sample count.

Abstract: The device includes a circuit for sector remapping having a CAM (Content Addressable Memory) unit, associated to and in data communication with a multiplexer unit. The CAM unit detects that a sector is defective, it provides the pre-programmed address of a replacing sector and it activates the multiplexer which performs the replacement. The defective sectors and the corresponding locations of the address map are therefore advantageously positioned to the rear to the addressing area. The addressing area is consequently continuous, thus allowing the information to be easily stored and retrieved.

Abstract: A Design Failure Mode Effect Analysis (DFMEA) method analyzes faults and failures in the design phase of electronic devices. A data-entry mask is used for recording some information concerning the performed analysis and a portion of the recording form is displayed to a user in an electronic display format. The method detects and records past design problems and their corresponding solutions, by a DFMEA method using the data-entry mask form; associates keywords in a database with each problem; associates data concerning each of the design problems, in the same database, including information concerning past fails occurred in similar applications; detects major changes and/or innovations, as well as any improved block or part of a new device with respect to other devices, thereby postulating possible new problems introduced by the new device; and records the new problems and their possible solutions, by the DFMEA method and using the form.

Abstract: The invention relates to a method of expanding the functional capabilities of portable electronic devices with user friendly modes, wherein a host device is associated a quick-connect function-expanding module. In this method, at each installation of a given module, the functional expansion module and the host device recognize each other; on first installation of a given module in the host device, a series of checking operations are carried out automatically; the user can select to activate the available expansion; and once a given application is selected, the configuration and functions required for each application are stored.

Abstract: A method for controlling a vehicle semi-active suspension system comprising at least one suspension, providing for: detecting vehicle dynamic quantities during the vehicle ride; using the detected dynamic quantities, determining an index of ride comfort and an index of roadholding; applying a weight factor to the index of ride comfort and to the index of roadholding and, based on a Sky Hook control model, determining a target damping force characteristics for the at least one suspension of the suspension system; controlling the at least one suspension to put the respective damping force characteristics in accordance with the calculated target damping force characteristics. The weight factor is calculated dynamically during the vehicle ride, by means of a fuzzy calculation on the detected vehicle dynamic quantities.

Abstract: A converter circuit for performing transfer of control logic signals between a first device and a second device in connection with an interconnection bus, the first device operating at the frequency of a first clock signal and the second device operating at the frequency of a second clock signal. The clock frequencies may be in a first ratio to one another corresponding to unity, as well as in a second and a third ratio. The converter circuit includes manipulation circuit elements which define respective propagation paths through the converter circuit for control signals. A logic network may assume three states, corresponding, respectively, to the first, second and third ratios between the frequencies of the clock signals, selectively interposing the manipulation elements in the propagation paths.

Abstract: A hybrid inductive-capacitive charge pump provided with a driving stage that comprises a step-up converter and a buffer capacitor, and a cascade of charge pump stages; the first stage of the stage cascade is connected to a power supply and the last stage of the stage cascade is connected to an output of the charge pump circuit; the charge pump circuit comprises elements for activating alternately the charge pump stages, transferring charge from one stage of the cascade to the next stage of the cascade, each stage of the cascade of charge pumping stages comprising a pass transistor and a capacitor.

Abstract: A digital interface for driving at least one complementary pair of first and second power elements connected in an inverter configuration between first and second voltage references is provided. The digital interface includes a first input terminal for receiving a PWM input signal, a first counter stage connected to the first input terminal, and a second counter stage connected to an output of the first counter stage. A toggle stage is connected to the first input terminal and to an output of the second counter stage. A first output terminal is connected to an output of the toggle stage, and is to be connected to a control terminal of the first power element. A second output terminal is connected to the output of the first counter stage for receiving a delayed PWM output signal therefrom, and is to be connected to a control terminal of the second power element. The toggle stage generates a second PWM output signal for the first output terminal.

Abstract: A semiconductor memory device includes a plurality of memory cells arranged according to a plurality of rows and a plurality of columns. The memory devices further includes a plurality of bit lines, each bit line being associated with a respective column of the plurality, and a selecting structure of the bit lines, to select at least one among the bit lines, keeping the remaining bit lines unselected. The memory device further includes a voltage clamping circuit structured to cause the clamping at a prescribed voltage of the unselected bit lines adjacent to a selected bit line during an access operation to the memory.

Abstract: A method and an electronic device for stabilizing the voltage on the drain terminals of multi-level non-volatile memory cells during programming thereof. The voltage is provided by a drain voltage regulator having an output connected to the drain terminals at a common circuit node by a metal line conduction path having a parasitic intrinsic resistance. A feedback path is advantageously provided between the common circuit node and an input of the regulator.

Abstract: A device and method for programming an electrically programmable memory accesses a group of memory cells (MC1–MCk) of the memory to ascertain a programming state thereof (401,407;503,509a,513a); applies a programming pulse to those memory cells in the group whose programming state is not ascertained to correspond to a desired programming state (405;507a,509c,513c); and repeats the steps of accessing and applying for the memory cells in the group whose programming state is not ascertained (411;509b,513b). After the programming state of a prescribed number of memory cells in the group has been ascertained, the memory cells in the group are accessed again and the programming state of the memory cells whose programming state was previously ascertained is re-ascertained (413,415;515). At least one additional programming pulse is applied to those memory cells in the group whose programming state is not re-ascertained (405;507a,509c,513c).

Abstract: In order to speed up the search for a data item in the memory and simplify the circuit structure of the memory, with each row of cells there is associated a ground control line, a ground line and a match control line. Furthermore, with every row of cells there is associated a search activation terminal and a match indication terminal.

Abstract: A memory cell includes a volatile circuit operable to store first data, and a nonvolatile circuit coupled to the volatile circuit and operable to store second data. The volatile circuit is operable to program the nonvolatile circuit with the first data, and the nonvolatile circuit is operable to program the volatile circuit with the second data.

Abstract: A continuous-time filter comprising at least one amplifier and at least one passive element. The amplifier comprises at least one input terminal and at least one output terminal and the passive element is positioned between the terminals. In addition the amplifier is provided with a transconductance gain. The filter comprises circuit means suitable for correlating the transconductance gain of the amplifier with the passive element.

Abstract: A neuro-fuzzy filter device that implements a moving-average filtering technique in which the weights for final reconstruction of the signal are calculated in a neuro-fuzzy network according to specific fuzzy rules. The fuzzy rules operate on three signal features for each input sample. The signal features are correlated to the position of the sample in the considered sample window, to the difference between a sample and the sample at the center of the window, and to the difference between a sample and the average of the samples in the window. The filter device for the analysis of a voice signal includes a bank of neuro-fuzzy filters. The signal is split into a number of sub-bands, according to wavelet theory, using a bank of analysis filters including a pair of FIR QMFs and a pair of downsamplers; each sub-band signal is filtered by a neuro-fuzzy filter, and then the various sub-bands are reconstructed by a bank of synthesis filters including a pair of upsamplers, a pair of FIR QMFs, and an adder node.

Abstract: A semiconductor memory comprises a plurality of memory cells, for example Flash memory cells, arranged in a plurality of lines, and a plurality of memory cell access signal lines, each one associated with at least one respective line of memory cells, for accessing the memory cells of the at least one respective line of memory cells; each signal line has a capacitance intrinsically associated therewith. A plurality of volatile memory cells is provided, each having a capacitive storage element. Each volatile memory cell is associated with a respective signal line, and the respective capacitive storage element formed by the capacitance intrinsically associated with the respective signal lines. In particular, the parasitic capacitances associated with bit lines of a matrix of memory cells can be exploited as capacitive storage elements.