Abstract: Subdivision per basic color channels of grey level data generated by a color sensor is no longer required according to a novel color interpolation method of an image acquired by a digital color sensor generating grey levels for each image pixel as a function of the filter applied to the sensor by interpolating the values of missing colors of each image pixel for generating triplets or pairs of values of primary colors or complementary base hues for each image pixel. The method may include calculating spatial variation gradients of primary colors or complementary base hues for each image pixel and storing the information of directional variation of primary color or complementary base hue in look-up tables pertaining to each pixel.

Abstract: A method for manufacturing semiconductor-integrated electronic circuits includes: depositing an auxiliary layer on a substrate; depositing a layer of screening material on the auxiliary layer; selectively removing the layer of screening material to provide a first opening in the layer of screening material and expose an area of the auxiliary layer; and removing this area of the auxiliary layer to form a second opening in the auxiliary layer, whose cross-section narrows toward the substrate to expose an area of the substrate being smaller than the area exposed by the first opening.

Abstract: A phase-locked loop includes an oscillator, a phase detector coupled to the oscillator, a charge pump coupled to the phase detector, a filter coupled to the charge pump, a voltage controlled oscillator, and a fractional frequency divider. The voltage controlled oscillator sends a VCO signal to the divider which sends an output signal to the phase detector. The divider comprises a prescaler that divides the VCO signal by an integer number and the divider emits a first signal representing the result of the division. The phase-locked loop comprises an accumulator coupled to the divider and a digital-analog converter that receives the first signal and outputs a DAC signal aligned with the first signal. The phase-locked loop comprises a circuit coupled to the digital-analog converter and to the prescaler to synchronize the DAC signal with a signal output from the prescaler.

Abstract: The optical communication module can be coupled to at least one optical fiber and includes at least one optoelectronic device, a base portion, and a cover portion which can be connected to the base portion to define an internal chamber to house the optoelectronic device. The cover portion includes at least one window to couple at least one optical signal between the at least one device and the optical fiber. The module further includes a plate, substantially transparent to the optical signal, having a first side facing the cover portion and a second side facing the internal chamber, the first plate substantially enabling sealing of the window. A shielding plate can be connected to the second side and provided with at least one opening substantially aligned with the window to enable passage of the optical signal.

Abstract: A method is for compressing a digital image that is made up of a matrix of elements, with each element including a plurality of digital components of different types for representing a pixel. The method includes splitting the digital image into a plurality of blocks, and calculating for each block a group of DCT coefficients for the components of each type, and quantizing the DCT coefficients of each block using a corresponding quantization table scaled by a gain factor for achieving a target compression factor. The method further includes determining at least one energy measure of the digital image, and estimating the gain factor as a function of the at least one energy measure. The function is determined experimentally according to the target compression factor.

Abstract: A finite impulse response (FIR) filter for implementing a Hilbert transform is provided. The FIR filter includes a plurality of programmable delay cells connected in cascade between an input terminal of the FIR filter and an output terminal of the FIR filter. Each programmable delay cell has associated therewith a constant filter coefficient and a programmable delay coefficient. The FIR filter is also applicable for processing signals originated by the reading of data from a magnetic storage media which employs perpendicular recording.

Abstract: A detector detects timing in a digital data flow with a bit-time equal to T. A first circuit generates four local timing signals each having periods substantially equal to the bit-time. Each of the four local timing signals are out of phase with one another by ¼ period. A second circuit samples the four local timing signals upon each transition of a first type for determining, based upon the sampling, whether two of the four local timing signals forming a pair of reference signals that are out of phase by ½ period are advanced or delayed relative to the timing of the data flow. The second circuit controls the first circuit for delaying or advancing the four local timing signals based upon the pair of reference signals.

Abstract: A circuit is proposed for driving a memory line controlling at least one memory cell of a non-volatile memory device, the circuit being responsive to a first and a second selection signals, each one suitable to assume a first logic value or a second logic value, wherein the circuit includes a first level shifter for converting the first selection signal into a first operative signal and a second level shifter for converting the second selection signal into a second operative signal, each level shifter including first shifting means for shifting one of the logic values of the corresponding selection signal to a first bias voltage, and a selector for applying the first operative signal or a second bias voltage to the memory line according to the second operative signal; in the circuit of the invention each level shifter further includes second shifting means for shifting another of the logic values of the corresponding selection signal to the second bias voltage.

Abstract: The timing system includes a plurality of timing units interconnected to perform a count operation. Software programmable registers interconnect the plurality of timing units, and a control circuit generates a clock signal for the plurality of timing units. The control circuit includes an interface for connection to an external bus to receive and transmit data.

Abstract: The method for manufacturing a micromechanical switch includes manufacturing a hanging bar, on a first semiconductor substrate, equipped at an end thereof with a contact electrode, and a frame projecting from the first semiconductor substrate. A second semiconductor substrate with conductive tracks includes a second input/output electrode and a third starting electrode, and first and second spacers electrically connected to the conductive tracks. The frame is abutted with the first spacers so that the fourth contact electrode abuts on the second input/output electrode in response to an electrical signal provided to the hanging bar by the third starting electrode.

Abstract: A driving circuit is provided for a control terminal of a bipolar transistor in an emitter-switching configuration. The emitter-switching configuration is between a resonant load and a voltage reference. The driving circuit includes at least one capacitor between the control terminal of the bipolar transistor and the voltage reference. The driving circuit further includes an additional resonance capacitor between a collector terminal of the bipolar transistor and a circuit node, a first diode between the circuit node and the control terminal, and a second diode between the circuit node and the voltage reference.

Abstract: A programmable oscillator comprises a capacitor; a current generator couplable to said capacitor that generates a charging current of said capacitor; further comprising at least one resistance coupled to said capacitor; a comparator coupled to said capacitor for comparing a voltage at the terminals of said capacitor with a prefixed reference voltage and for generating an output signal; a first switch, controlled by said output signal, coupled to said capacitor that creates a current path able to facilitate the discharging of said capacitor.

Abstract: A semiconductor memory system comprising a memory matrix including a plurality of memory cells arranged in rows and columns and connected to a plurality of column lines, each memory cell of the same column having a first and a second terminal connected to a first and a second column line respectively. Furthermore, the memory system comprises a first and a second conduction line which can be connected to said first and second column lines, and generating means provided with at least a first and a second output line, making available a first and a second reading/writing voltage to said first and second terminal respectively. The memory system also comprises at least a first and a second selection transistor connected to the same command line and having corresponding operative terminals connected directly to the first and to the second output lines respectively and corresponding cell terminals connected directly to the first and to the second conduction lines respectively.

Abstract: A control circuit is connected to a plurality of driving stages. Each driving stage includes a high-voltage terminal for driving an inductive load. The control circuit is provided with a corresponding plurality of control stages. These control stages are integrated in a single semiconductor body and connected each to the high-voltage terminal of a respective driving stage.

Abstract: An MOS device has a stack and a passivation layer covering the stack. The stack is formed by a first polysilicon region and by a second polysilicon region arranged on top of one another and separated by an intermediate dielectric region. An electrical connection region, formed by a column structure substantially free of steps, extends through the passivation layer, the second polysilicon region and the intermediate dielectric region, and terminates in contact with the first polysilicon region so as to electrically contacting the first polysilicon region and the second polysilicon region. Fabrication of the electrical connection region requires just one mask.

Abstract: A phase change memory includes a temperature sensor having a resistance variable with temperature with the same law as a phase-change storage element. The temperature sensor is formed by a resistor of chalcogenic material furnishing an electrical quantity that reproduces the relationship between the resistance of a phase change memory cell and temperature; the electrical quantity is processed so as to generate reference quantities as necessary for writing and reading the memory cells. The chalcogenic resistor has the same structure as a memory cell and is programmed with precision, preferably in the reset state.

Abstract: A boot method for a data control unit downloads boot information from a nonvolatile memory into a temporary buffer of a boot-activation unit. A processing unit is activated by the boot-activation unit; a boot code is executed by the processing unit; and an operating code is downloaded from the nonvolatile memory into a volatile memory through the boot-activation unit. To correct possible errors in the block of the nonvolatile memory containing information and boot codes, the boot-activation unit verifies whether the boot information downloaded into its volatile memory has a critical-error condition and activates a spare memory portion of the nonvolatile memory in presence of the critical-error condition.

Abstract: The conversion into a progressive format of digital images organized in half-frames or fields with interlaced lines or rows envisages selecting successive lines in one or more of said fields and reconstructing by pixels an image line set between the interlaced lines selected. The reconstruction operation obtains the image by creating a set of candidate patterns associated to the work window by selecting the patterns to be considered within the window. Next, applying to the patterns of the aforesaid set a first cost function which is representative of the correlations between pairs of pixels. Applying to the patterns of the aforesaid set a second cost function which is representative of the non-correlations between pairs of pixels. Selecting, for each candidate pattern, respective internal correlations and external non-correlations, calculating corresponding scores for the candidate patterns using the aforesaid first cost function.

Abstract: A comparator for comparing binary numbers with N bits, where N>1, in which a plurality (200) of bit-to-bit comparators supplies a plurality of equality-difference signals, arranged in order of decreasing significance of the bits compared, to a matrix of transistors, arranged in 4 columns (201, 202, 203, 204) of N rows of transistors arranged in order, so as to control the gates of the transistors; the matrix, which receives, at the sources of the transistors of two (203, 204) of the columns, the signals representative of the bits of one of the numbers compared and their negated signals, is interconnected in a manner such as to identify the most significant difference by a simultaneous logic process, and to decide, on the basis of the bit signals received, which of the binary numbers is greater than, or greater than or equal to the other, presenting the outcome of the decision at an output (U2) within a very short time and with the use of much fewer active components than are required by conventional combin

Abstract: A method for error control in multilevel memory cells storing a configurable number of bits. The error control is performed using an error-control code which operates, in the encoding phase, on b-bit binary strings made up of k symbols of r-bit data. When the memory cells store a number r of bits, a data symbol is formed only with the data bits stored in a memory cell. When the memory cells store a number s of bits smaller than r, a data symbol is formed with the data bits stored in a memory cell and with r-s bits having a pre-determined logic value, in which the data bits stored in the memory cell are arranged in the least significant part of the data symbol, and the r-s bits having a pre-determined logic value are arranged in the most significant part of the data symbol.