Abstract: A decoupler that allows for asynchronous communication between two synchronous IP cores. The decoupler reduces or eliminates the need for distribution and balancing of the clock. More specifically, the decoupler provides the ability to decouple an IP core from the interconnect clock domain, thereby reducing the need for clock balancing. The decoupler is inserted between a source IP core and a target IP core, and may include two interfaces, one located near the source and another located near the target. Synchronous data messages are converted to asynchronous data messages for transmission across a physical connection. Once the asynchronous data message is received by the interface near the target or source, the data message is converted back to a synchronous message.

Abstract: A method for manufacturing electrically non-active structures for an electronic circuit integrated on a semiconductor substrate is provided, with the electronic circuit including first and second electrically active structures. The method includes inserting the electrically non-active structures in the electronic circuit to make uniform a surface above the semiconductor substrate. The inserting includes identifying, among the electrically non-active structures, a first group of electrically non-active structures to be adjacent the first and second electrically active structures, and identifying, among the electrically non-active structures, a second group of electrically non-active structures not adjacent to the first and second electrically active structures. The method further includes defining, on the semiconductor substrate, the first and second groups of electrically non-active structures through different photolithographic steps.

Abstract: A basic stage for a charge pump circuit having at least an input terminal and an output terminal and comprising: at least a first inverter inserted between said input and output terminals and comprising a first complementary pair of transistors, defining a first internal node, at least a second inverter inserted between said input and output terminals and comprising a second complementary pair of transistors, defining a second internal node, respective first and second capacitors connected to said first and second internal nodes and receiving first and second driving signals; the first and second pairs of transistors having the control terminals cross-connected to the second and first internal nodes. Advantageously, the basic stage comprises at least a first biasing structure connected to the first and second internal nodes and comprising first and second biasing transistors, which are respectively coupled to said first and second inverters.

Abstract: A digital control apparatus for a switching DC-DC converter includes at least one power transistor and is able to provide a regulated output voltage on a load. The apparatus includes digital control having a reference digital input signal and provides a modulating signal to a PWM device to which is input the modulating signal and which provides an output square wave signal for driving the power transistor of the DC-DC converter such that there is non-linear modulation only when the value of a signal on the load is lower or higher than a prefixed value range.

Abstract: A resonant micro-electro-mechanical system includes a microstructure having a mass which is free to oscillate in accordance with a predetermined degree of freedom, and a driving device coupled to the mass for maintaining the mass in oscillation at a resonance frequency. The driving device includes a differential sense amplifier supplying first signals indicative of a velocity of oscillation of the mass, and an actuation and control stage supplying second signals for driving the mass on the basis of the first signals. The driving device moreover includes a filtering circuit of a high-pass type, which is connected between the differential sense amplifier and the actuation and control stage, and has a bandpass that includes the resonance frequency.

Abstract: An electrically programmable memory device is proposed including: a matrix of memory cells arranged in a plurality of memory arrays and at least one redundancy array; and a substituting structure that substitutes the use of each memory array with the use of one of the at least one redundancy array in response to a failure of the memory array, wherein the memory arrays are grouped into at least one set. The substituting structure includes: a structure for associating each set with a predetermined one of the at least one redundancy array; a flag for each memory array indicative of the failure of the memory array; and a selecting for enabling each memory array or the associated redundancy array according to the corresponding flag.

Abstract: A micro-electro-mechanical sensor includes a microstructure having a mass which is movable with respect to a rest position, according to a predetermined degree of freedom, and a displacement-detecting device for detecting a displacement of the mass according to the predetermined degree of freedom. The displacement-detecting device includes a force feedback loop of a purely analog type, which supplies electrostatic forces tending to restore the mass to the rest position in response to a displacement of the mass according to the predetermined degree of freedom.

Abstract: A Common Rail injection system of an endothermic engine, the injection system including at least one fuel pressure accumulating tank, of the rail type, having an input in fluid communication with a high-pressure pump and a plurality of outputs for feeding corresponding injectors by using pressure regulating means connected and depending on an electronic control unit. Advantageously a virtual pressure sensor includes a fluid-dynamic model of the accumulating tank suitable to estimate and to obtain fluid pressure values used by the electronic control unit for driving the injection means of the Common Rail injection system.

Abstract: A switching voltage regulator provides a regulated voltage at an output terminal. The switching voltage regulator includes a MOS transistor having a non-drivable terminal coupled with the output terminal and a control circuit receiving a signal that is representative of the current signal flowing in the MOS transistor. The control circuit includes a compensation device adapted for cancelling the thermal variation of the signal that is representative of the current signal flowing in the MOS transistor.

Abstract: A method for manufacturing semiconductor-integrated electronic circuits includes: depositing an auxiliary layer on a substrate; depositing a layer of screening material on the auxiliary layer; selectively removing the layer of screening material to provide a first opening in the layer of screening material and expose an area of the auxiliary layer; and removing this area of the auxiliary layer to form a second opening in the auxiliary layer, whose cross-section narrows toward the substrate to expose an area of the substrate being smaller than the area exposed by the first opening.

Abstract: A managing system manages a plurality of VRMs associated with a plurality of microprocessors and connected in parallel together between first and second voltage references, the VRMs having output terminals connected together and arranged to communicate over a common bus. The managing system includes an error amplifier being input an output voltage signal from the VRM plurality, a reference voltage, and a droop voltage produced through an equivalent droop resistor receiving an output current signal from the VRM plurality and being connected to the common bus. The error amplifier effects a comparison of the input signals to generate a control voltage signal to the VRM plurality. Advantageously, the managing system comprises a controller connected to the equivalent droop resistor.

Abstract: A read/verify circuit for multilevel memory cells includes: a read terminal selectively connectable to a plurality of array cells, having respective array threshold voltages; a plurality of reference cells, having respective reference threshold voltages; and a plurality of threshold-detection circuits, for detecting the array thresholds and the reference thresholds. In particular, the read terminal and the reference cells are each connected to a respective threshold-detection circuit. Each threshold-detection circuit is provided with a respective detector element of a resistive type, set so as to be traversed by a current response to turning-on of the respective array cell or reference cell associated thereto.

Abstract: A built-in self-test and self-repair structure (BISR) of memory arrays embedded in an integrated device includes at least a test block (BIST) programmable to execute on a respective memory array of the device any of a certain number of test algorithms, and a self-repair block that includes a column address generator processing the faulty address information for allocating redundant resources of the tested memory array. The BISR may further include a redundancy register on which final redundancy information is loaded at each power-on of the device and control logic for managing data transfer from external circuitry to the built-in self-test and self-repair structure (BISR) and vice versa. The BIST structure serves any number of embedded memory arrays even of different types and sizes.

Abstract: The method is for receiving an OFDM signal according to which, during a frequency translation phase, there is introduced a phase and gain imbalance between the phase and quadrature components thereof, and a frequency offset relative to a main carrier of the OFDM signal. The method involves a compensation of the effects of the imbalance even in the presence of the frequency offset and provides a reference signal indicative of the effect of the imbalance and according to which a process is carried out to reduce the effect of the imbalance itself.

Abstract: The invention provides a protocol cycle during which a memory address and all the data bytes to be written are transmitted, and the writing process is carried out only once for all the transmitted data bytes, by writing a first byte in the memory sector corresponding to a first address generated by resetting to zero the 2 least significant bits of the transmitted address and all the other transmitted bytes in successive addresses. The method includes writing a certain number N of data bytes, in consecutive memory addresses in a memory array of a memory device, and includes unprotecting the memory sectors in which data are to be written, communicating the programming command to the memory device, communicating to the memory device the bits to be stored and specifying a relative memory address of a sector to write in, and writing the data bits in the memory.

Abstract: The present invention refers to a charge pump system supplied by a direct voltage signal and supplying on the output terminal a voltage signal with a higher value of said direct voltage signal.

Abstract: A coprocessor circuit for processing image data in digital form, having a motion vector controller block for generating, starting from the image data, motion vector values that include predictor data and macroblock data relating to a current macroblock of the image data to be estimated and being adapted to be stored at respective memory addresses. Also included is an address generator block for extracting respective addresses from the motion vector values, a predictor fetch block for retrieving predictor data based on respective addresses extracted by the address generator block, a current macroblock fetch and distengine block for retrieving macroblock data based on respective addresses extracted by the address generator block and for processing the macroblock data according to a given function, and a decision block for collecting the retrieved data as partial results and selecting the best result therefrom.

Abstract: A common mode control circuit reduces abrupt voltage changes at the outputs of a pair of amplifiers which, in turn, reduces EMI and distortions that occur when the correlation between the signals fed to the four channels of an audio system diminishes. The common mode control circuit generates for each amplifier a reference potential that is a saturated replica of the respective differential input signal of the amplifier that saturates when the amplifier switches to a bridge configuration.

Abstract: A fast method of color interpolation of pixels of an image acquired by a color filtered digital sensor uses a very simple cost function that nevertheless produce interpolated images of good quality. The cost function is computationally simpler because it does not require the calculation of powers and square roots. The triangulation algorithm may be executed in far less time, while practically ensuring the same performance. The triangulation algorithm on average may use only two iteration steps. The interpolation process may be followed by an anti-aliasing processing that effectively removes color artifacts.

Abstract: The process comprises the steps of forming, on top of a semiconductor material wafer, a holed mask having a lattice structure and comprising a plurality of openings each having a substantially square shape and a side with an inclination of 45° with respect to the flat of the wafer; carrying out an anisotropic etch in TMAH of the wafer, using said holed mask, thus forming a cavity, the cross section of which has the shape of an upside-down isosceles trapezium; and carrying out a chemical vapor deposition using TEOS, thus forming a TEOS layer which completely closes the openings of the holed mask and defines a diaphragm overlying the cavity and on which a suspended integrated structure can subsequently be manufactured.