Abstract: A nonvolatile phase change memory device including a memory array formed by memory cells arranged in rows and columns, word lines connected to first terminals of memory cells arranged on the same row, and bit lines connected to second terminals of memory cells arranged on the same column; a row decoder coupled to the memory array to bias the word lines; a column decoder coupled to the memory array to bias the bit lines; and a biasing circuit coupled to the row decoder and to the column decoder to supply a first biasing voltage and a second biasing voltage to the terminals of an addressed memory cell, wherein the first biasing voltage is a positive biasing voltage and the second biasing voltage is a negative biasing voltage.

Abstract: A memory has one bus for data, addresses, and commands. A data register is coupled to the bus to store the data written to and read from the memory, a command register is coupled to the bus for receiving memory commands, and an address register is coupled to the bus to address the memory. The memory also includes an Error Correction Code circuit for calculating an ECC. The memory is configured to be responsive to external commands for controlling the operation of the ECC circuit for reading or writing of the ECC that are separate from external commands controlling reads or writes of the memory data. The memory may also include a status register that stores information regarding the passing or failing of the ECC.

Abstract: An RGB digital video signal destined to be displayed on a display such as a liquid crystal display (LCD) is converted from the RGB color space to the YUV color space. The signal converted into the YUV color space is subjected to at least a processing operation selected among a sub-sampling operation (24) and a data compression operation (26). The signal is then stored in a memory and the signal read from said memory (12) is then subjected to at least a return operation (28, 30) complementary to the aforesaid processing operation (24, 26). The signal subjected to the aforesaid return operation is lastly reconverted from the YUV color space to the RGB color space, thus being susceptible to be displayed on the display.

Abstract: The system can be used for the automatic analysis of images, including a matrix of spots, such as images of DNA microarrays after hybridization. The system can be associated—and preferably integrated in a single monolithic component implementing VLSI CMOS technology—to a sensor for acquiring the images. The system includes a circuit for processing the signals corresponding to the images, configured according to a cellular neural network (CNN) architecture for the parallel analogue processing of signals.

Abstract: A hosting structure of nanometric components is described advantageously comprising: a substrate; n array levels on said substrate, with n?2, arranged consecutively on growing and parallel planes, each including a plurality of conductive spacers alternated with a plurality of insulating spacers and substantially perpendicular to said substrate, with definition between consecutive conductive spacers of at least a gap, conductive spacers of consecutive array levels lying on distinct and parallel planes, said gaps of different array levels being at least partially aligned along a direction substantially perpendicular to said substrate with definition of a plurality of transversal hosting seats extended along said direction and suitable for hosting at least a nanometric component. A nanometric electronic device is also described comprising such a hosting structure and a method for realizing it.

Abstract: Method for manufacturing a hosting structure of nanometric elements comprising the steps of depositing on an upper surface of a substrate, of a first material, a block-seed having at least one side wall. Depositing on at least one portion of sad surface and on the block-seed a first layer, of predetermined thickness of a second material, and subsequently selectively and anisotropically etching it to form a spacer-seed adjacent to the side wall. The cycle of deposition and selective etching steps of a predetermined material are repeated n times (n?2), with at least one spacer formed in each cycle. This predetermined material is different for each pair of consecutive depositions. The above n steps provides at least one multilayer body. Further selective etching removes every other spacers to provide a plurality of nanometric hosting seats, which forms contact terminals for a plurality of molecular transistors hosted in said hosting seats.

Abstract: The block de-interleaving system includes an input for receiving a set of time-aligned blocks or interleaved data, physical memory unit, and a de-interleaving block for writing the blocks in the memory in a first predetermined manner and reading the blocks from the memory in a second predetermined manner to de-interleave the data of the blocks. The physical memory unit may include several different physical memories, and the de-interleaving block is adapted to completely write and read a block into and from one physical elementary memory.

Abstract: In the method, the membership image is produced through a multi-stage process that contemplates a first punctual classification stage generating a rough membership image, followed by a low-pass filtering of regionalization of the image through a down-sampling of the image followed by an up-sampling of the image, and in a further step of merging the regions that overcomes the superposition effects induced by the low-pass filtering operation. The so generated membership image contains semantic information of the input image that may be used for effectively implementing an adaptive correction/improvement of the color of the input image. For an adaptive correction/improvement of the color, the encoded data of the generated membership image is fed in parallel to the data of the real image to an adaptive modification block of the color of the image pixels.

Abstract: An electronic semiconductor device has a sublithographic contact area between a first conductive region and a second conductive region. The first conductive region is cup-shaped and has vertical walls which extend, in top plan view, along a closed line of elongated shape. One of the walls of the first conductive region forms a first thin portion and has a first dimension in a first direction. The second conductive region has a second thin portion having a second sublithographic dimension in a second direction transverse to the first dimension. The first and the second conductive regions are in direct electrical contact at their thin portions and form the sublithographic contact area. The elongated shape is chosen between rectangular and oval elongated in the first direction. Thereby, the dimensions of the contact area remain approximately constant even in presence of a small misalignment between the masks defining the conductive regions.

Abstract: A process for manufacturing an array of cells, including: implanting, in a body of semiconductor material of a first conductivity type, a common conduction region of the first conductivity type; forming, in the body, above the common conduction region, a plurality of active area regions of a second conductivity type and a first doping level; forming, on top of the body, an insulating layer having first and second openings; implanting first portions of the active area regions through the first openings with a doping agent of the first conductivity type, thereby forming, in the active area regions, second conduction regions of the first conductivity type; implanting second portions of the active area regions through the second openings with a doping agent of the second conductivity type, thereby forming control contact regions of the second conductivity type and a second doping level, higher than the first doping level; forming, on top of the body, a plurality of storage components, each storage component havin

Abstract: In an actuator device for hard disks a suspension element carries a slider that is subject to undesired vibrations which give rise to rotations of the slider with respect to a nominal position. An electrostatically controlled position-control structure is arranged between the suspension and the slider and is controlled in an active way so as to generate torsions of the platform that counter the undesired rotations. The position-control structure comprises a platform of conductive material and control electrodes arranged underneath the platform. The platform is connected to a load-bearing structure by spring elements that enable movements of roll and pitch. Four control electrodes are arranged according to the quadrants of a square and can be selectively biased for generating electrical forces acting on the platform.

Abstract: In order to generate, starting from an input MPEG bitstream, an output MPEG bitstream having at least one entity chosen among syntax, resolution, and bitrate modified with respect to the input bitstream, first portions and second portions are distinguished in the input bitstream, which respectively substantially do not affect and do affect the variation in bitrate. When at least one between the syntax and the resolution is to be modified, the first portions of the input bitstream are subjected to the required translation, then transferring said first portions subjected to syntax and/or resolution translation to the output bitstream. When the resolution is left unaltered, the second portions are transferred from the input bitstream to the output bitstream in the substantial absence of processing operations. When the resolution is changed, the second portions of the input bitstream are subjected to a filtering in the domain of the discrete cosine transform.

Abstract: The microreactor is completely integrated and is formed by a semiconductor body having a surface and housing at least one buried channel accessible from the surface of the semiconductor body through two trenches. A heating element extends above the surface over the channel and a resist region extends above the heating element and defines an inlet reservoir and an outlet reservoir. The reservoirs are connected to the trenches and have, in cross-section, a larger area than the trenches. The outlet reservoir has a larger area than the inlet reservoir. A sensing electrode extends above the surface and inside the outlet reservoir.

Abstract: A process for manufacturing a byte selection transistor for a matrix of non volatile memory cells organised in rows and columns integrated on a semiconductor substrate, each memory cell comprising a floating gate transistor and a selection transistor, the process providing the following steps: defining on a same semiconductor substrate respective active areas for the byte selection transistor, for the floating gate transistor and for the selection transistor split by portions of insulating layer; depositing a multilayer structure comprising at least a gate oxide layer, a first polysilicon layer, a dielectric layer on the whole substrate and a second polysilicon layer, characterised in that it comprises the following steps: removing through a traditional photolithographic technique the multilayer structure to form at least a couple of two bands developing substantially in a parallel way to the columns of the matrix of memory cells, the first band being effective to define the gate regions of the byte selection

Abstract: The semiconductor inertial sensor is formed by a rotor element and a stator element electrostatically coupled together. The rotor element is formed by a suspended mass and by a plurality of mobile electrodes extending from the suspended mass. The stator element is formed by a plurality of fixed electrodes facing respective mobile electrodes. The suspended mass is supported by elastic suspension elements. The suspended mass has a first, larger, thickness, and the elastic suspension elements have a second thickness, smaller than the first thickness.

Abstract: The described integrated planar optical structure comprises a principal waveguide having a core and a cladding that define a first light path ad means sensitive to the light radiated into the cladding comprising at least one secondary waveguide having a core and a cladding that define a second light path. The secondary waveguide has an entry situated in the cladding of the principal waveguide at such a distance from the core of the latter as not to interfere with the propagation of the light along the first optical path and a core section that becomes greater in a first part from the entry onwards to collect the light energy radiated into the cladding. Also described are a system for monitoring the light energy emitted by a source and an optical attenuator that comprise the aforesaid optical structure.

Abstract: A method is described for generating a reference current for sense amplifiers connected to cells of a memory matrix comprising the steps of generating a first reference current analog signal through a reference cell, performing an analog-to-digital conversion of the first analog signal into a reference current digital signal, sending the digital signal on a connection line to the sense amplifiers, and performing a digital-to-analog conversion of the digital signal into a second reference current analog signal to be applied as reference current to the sense amplifiers.

Abstract: A process is disclosed for forming, on a common semiconductor substrate, CMOS transistors and vertical or lateral MOS transistors on at least first and second portions, respectively, of the substrate. A first dielectric layer is formed on the substrate. A first semiconductor material layer is then formed on the first dielectric layer, in the first portion. A stack structure comprising a second dielectric layer, second semiconductor layer, and low-resistance layer is then formed over the substrate. First ports are defined in the second semiconductor layer and the low-resistance layer to provide gate regions of the vertical or lateral MOS transistors. The second semiconductor layer and the low-resistance layer are then removed from the first portion of the substrate by using the second dielectric layer as a screen. Second ports in the second dielectric layer and the second semiconductor layer are then defined to provide gate regions for the CMOS transistors.

Abstract: A phase-locked loop circuit provides an output signal having a frequency depending on the frequency of a reference signal. The circuit includes a feedback circuit that derives a feedback signal from the output signal, a phase frequency detector that provides a control signal indicative of a phase difference between the reference signal and the feedback signal, a control circuit that controls the frequency of the output signal according to the control signal, and a conditioning circuit that conditions the control signal through a conditioning signal. The conditioning circuit includes a storage circuit that stores energy provided by the control signal and the conditioning signal during a first phase and transfers the accumulated energy to the control circuit during a second phase.

Abstract: A decoupler that allows for asynchronous communication between two synchronous IP cores. The decoupler reduces or eliminates the need for distribution and balancing of the clock. More specifically, the decoupler provides the ability to decouple an IP core from the interconnect clock domain, thereby reducing the need for clock balancing. The decoupler is inserted between a source IP core and a target IP core, and may include two interfaces, one located near the source and another located near the target. Synchronous data messages are converted to asynchronous data messages for transmission across a physical connection. Once the asynchronous data message is received by the interface near the target or source, the data message is converted back to a synchronous message.