Abstract: A method for transmitting on an optical connection an input data sequence having first and second logic states, includes encoding the input data sequence prior to transmission on the optical connection, where the encoding minimizes the first logic states in the encoded data sequence. The encoding includes: arranging the input data sequence in parallel on a number of bus lines; counting the first logic states in the input data sequence; comparing the counting result with a value equal to half of the lines; and logically inverting the input data sequence on the lines if the counting result is greater than half of the lines of the input data sequence. The method further includes: ordering values of the input data sequence; identifying the first value having the first logic state; and applying the encoding operation just to the ordered values subsequent to the first value having the first logic state.

Abstract: A boosted sampling circuit that is relatively straightforward to form is provided, as well as a corresponding method for driving the same. The input voltage applied to the boosted sampling circuit may be equal to a supply voltage or may be greater than a maximum voltage level allowed by the prior art circuits. This result is attained by connecting the control nodes of a plurality of switches to the input node while a first control phase is active, and by connecting a current terminal of another switch to a biasing voltage for protecting it from breakdowns.

Abstract: There is provided a digital data transmission system that includes a first unit transmitting a first MLT3 signal, a second unit receiving the first MLT3 signal, and transformers. The second unit includes an equalizer receiving the first MLT3 signal and outputting a second MLT3 signal that is input to a recovery module for the transmitted digital data, and a device placed in feedback to the equalizer. The device receives the second MLT3 signal and outputs a third low frequency signal that is added to the first MLT3 signal. The device has a translation block for the up or down or no translation of the second MLT3 signal according to the low or high or intermediate value of such signal, and a low pass filter receiving the signal output from the translation block and outputting the third signal containing the low frequency component of the second MLT3 signal.

Abstract: An amplifying stage having a first circuit positioned between a first and a second reference voltage and having a first transistor with a first non-drivable terminal connected with a current supply and a second transistor having a first non-drivable terminal connected with a second non-drivable terminal of the first transistor, and the current supply connected to the first reference voltage, and a second circuit connected to the first circuit and fed by a current proportional to the current supplied by the current supply. The second circuit has at least one input terminal and is connected to a load. The first circuit has a connection between the first transistor and a drivable terminal of the second transistor for adapting current that passes through the second transistor to be the same as current from the current supply and the voltage between the first transistor and ground is greater than a saturation voltage between non-drivable terminals of the first transistor.

Abstract: A planar inertial sensor includes a first region and a second region of semiconductor material. The second region is capacitively coupled, and mobile with respect to the first region. The second region extends in a plane and has second portions, which face respective first portions of the first region. Movement of the second region, relative to the first region, in any direction belonging to the plane modifies the distance between the second portions and the first portions, which in turn modifies a value of the capacitive coupling.

Abstract: A combined decoder reuses input/output RAM of a turbo-code decoding circuit as alpha-RAM or beta-RAM for a convolutional code decoding circuit. Additional operational units are used for both turbo-coding and convolutional coding. An effective harware folding scheme permits calculation of 256 states serially on 8 ACS units.

Abstract: A process wherein an insulating region is formed in a body at least around an array portion of a semiconductor body; a gate electrode of semiconductor material is formed on top of a circuitry portion of the semiconductor body; a first silicide protection mask is formed on top of the array portion; the gate electrode and the active areas of the circuitry portion are silicided and the first silicide protection mask is removed. The first silicide protection mask (is of polysilicon and is formed simultaneously with the gate electrode. A second silicide protection mask of dielectric material covering the first silicide protection mask is formed before silicidation of the gate electrode. The second silicide protection mask is formed simultaneously with spacers formed laterally to the gate electrode.

Abstract: The invention relates to a method for testing non-volatile memory devices that have at least one parallel communication interface, and a conventional matrix of non-volatile memory cells with respective reading, changing and erasing circuits, wherein during the testing procedure, a reading mode is entered for reading a memory location upon the rise edge of a control signal producing a corresponding ATD signal. Advantageously in the invention, a subsequent reading step is started also upon the fall edge of the control signal. In this way, at each cycle of the control signal two memory locations, instead of one as in the prior art, are read.

Abstract: Integrated microreactor, formed in a monolithic body and including a semiconductor material region and an insulating layer; a buried channel extending in the semiconductor material region; a first and a second access trench extending in the semiconductor material region and in the insulating layer, and in communication with the buried channel; a first and a second reservoir formed on top of the insulating layer and in communication with the first and the second access trench; a suspended diaphragm formed by the insulating layer, laterally to the buried channel; and a detection electrode, supported by the suspended diaphragm, above the insulating layer, and inside the second reservoir.

Abstract: Encoded digital symbols are transmitted via a first pair of antennas and at least one second pair of antennas. The sets of symbols used for the transmission via the second pair of antennas are re-ordered temporally into subsets of symbols with respect to the symbols used for the first pair of antennas. For the first pair of antennas, there is used a signal subjected to encoding with a code-division-multiple-access code and subjected to spreading with a spreading code, and, likewise, for the second pair or pairs of antennas there are used signals subjected to encoding with respective code-division-multiple-access code and subjected to spreading with a respective spreading code. At least one between the respective code-division-multiple-access code and the respective spreading code used for the transmission via the second pair of antennas is different from the code-division-multiple-access code and from the spreading code used for the transmission via the first pair of antennas.

Abstract: A vertical-current-flow resistive element includes a monolithic region having a first portion and a second portion arranged on top of one another and formed from a single material. The first portion has a first resistivity, and the second portion has a second resistivity, lower than the first resistivity. To this aim, a monolithic region with a uniform resistivity and a height greater than at least one of the other dimensions is first formed; then the resistivity of the first portion is increased by introducing, from the top, species that form a prevalently covalent bond with the conductive material of the monolithic region, so that the concentration of said species becomes higher in the first portion than in the second portion. Preferably, the conductive material is a binary or ternary alloy, chosen from among TiAl, TiSi, TiSi2, Ta, WSi, and the increase in resistivity is obtained by nitridation.

Abstract: An electronic semiconductor device has a sublithographic contact area between a first conductive region and a second conductive region. The first conductive region is cup-shaped and has vertical walls which extend, in top plan view, along a closed line of elongated shape. One of the walls of the first conductive region forms a first thin portion and has a first dimension in a first direction. The second conductive region has a second thin portion having a second sublithographic dimension in a second direction transverse to the first dimension. The first and the second conductive regions are in direct electrical contact at their thin portions and form the sublithographic contact area. The elongated shape is chosen between rectangular and oval elongated in the first direction. Thereby, the dimensions of the contact area remain approximately constant even in presence of a small misalignment between the masks defining the conductive regions.

Abstract: In a matrix of non volatile memory cells integrated on a semiconductor substrate, each memory cell includes a floating gate transistor and a selection transistor formed in a first active area, while each byte includes a byte selection transistor formed in a second active area separated from the first by portions of insulating layer. A portion of a multilayer structure including a gate oxide layer, a first polysilicon layer, a dielectric layer, and a second polysilicon layer extends over the byte selection and selection transistors, forming the gate regions thereof, and further extending on a portion of insulating layer. A conductive layer is formed in an opening in the second polysilicon and dielectric layers, over the portion of insulating layer, putting the first polysilicon layer in electric contact with the second polysilicon layer. Another portion of the multiplayer structure comprises the gate region of the floating gate transistor.

Abstract: A package houses at least one electro-optic active element for transmission using an optical fiber. The package has a bearing element for the at least one electro-optic active element. Advantageously, the package has a sandwich-like structure and includes a closing element associated with the bearing element using a suitable aligning and coupling device to define a hermetically closed housing seat. Moreover, the closing element houses a lens in axial alignment with the electro-optic active element. An electro-optic module includes the package associated with a casing having a receptacle housing an optical fiber.

Abstract: The electronic device is formed in a die including a body of semiconductor material having a first face covered by a covering structure and a second face. An integral thermal spreader of metal is grown galvanically on the second face during the manufacture of a wafer, prior to cutting into dice. The covering structure comprises a passivation region and a protective region of opaque polyimide; the protective region and the passivation region are opened above the contact pads for the passage of leads.

Abstract: An analog-to-digital converter with a pipeline architecture for converting an analog input signal into a digital output signal with a predefined resolution includes a plurality of stages, each stage having a circuit for converting an analog local signal into a digital local signal with a local resolution lower than the predefined resolution, a circuit for determining an analog residue indicative of a quantization error of the converting circuit, a circuit for amplifying the analog residue by an inter-stage gain corresponding to the local resolution to generate the analog local signal for a next stage, and a circuit for combining the digital local signals of all the stages into the digital output signal weighting each digital local signal according to a digital weight depending on the corresponding inter-stage gain.

Abstract: A fuel cell for an electrical load circuit includes a first monocrystalline silicon substrate and a positive half-cell formed therein, and a second monocrystalline silicon substrate and a positive half-cell formed therein. Each half-cell includes a microporous catalytic electrode permeable to a gas and connectable to the electrical load circuit. A cell area is defined on a surface of each respective monocrystalline silicon substrate, and includes a plurality of parallel trenches formed therein for receiving the gas to be fed to the respective microporous catalytic electrode. A cation exchange membrane separates the two microporous catalytic electrodes. Each half-cell includes a passageway for feeding the respective gas to the corresponding microporous catalytic electrode.

Abstract: A method for controlling programming voltage levels of non-volatile memory cells comprises: providing a resistive divider connected to a programming voltage reference and effective to generate at least one programming voltage level; and providing a reference cell crossed by a cell current. Advantageously according to an embodiment of the invention the cell current is applied to the resistive divider to correlate the programming voltage level to the intrinsic features of the reference cell. A programming voltage regulator of non-volatile memory cells comprises at least an input stage inserted between a first and a second voltage reference and connected to a reference memory cell, as well as, in correspondence with its output terminal, to a resistive divider, inserted in turn between a programming voltage reference and the second voltage reference and connected to at least an output terminal of the regulator, effective to supply the programming voltage to the non-volatile memory cells.

Abstract: External cavity laser with reflector in optical wave guide, particularly HDBR laser, with an active element comprising a semiconductor optical amplifying cavity having a low-reflectivity facet (3), for example a Semiconductor Optical Amplifier (SOA) with a facet (30) opposite to said low-reflectivity facet treated with a reflecting coating, or a Fabry-Perot laser, and an external reflector comprising a Bragg grating (70) formed in an optical wave guide (4) near a termination (5), facing said facet, of a segment (5, 6, 7) of said optical wave guide coupled with the facet. The grating has a spatial profile of modulation of the refraction index such that a corresponding optical reflectivity spectrum (A) has an optical bandwidth (W) sufficiently small around a prescribed laser oscillation mode wavelength (?c) for the laser to oscillate only on the prescribed mode and not on other oscillation modes even in conditions of high-frequency direct modulation.

Abstract: According to the multilevel programming method, each memory location can be programmed at a non-binary number of levels. The bits to be stored in the two locations are divided into two sets, wherein the first set defines a number of levels higher than the non-binary number of levels. During programming, if the first set of bits to be written corresponds to a number smaller than the non-binary number of levels, the first set of bits is written in the first location and the second set of bits is written in the second location; ifit is greater than the non-binary number of levels, the first set of bits is written in the second location and the second set of bits is written in the first location. The bits of the first set in the second location are stored in different levels with respect to the bits of the second set.