Abstract: An optimized method of computing the value of the degree of membership of a fuzzy variable defined within a universe of discourse that is discreted into a finite number of points by way of a membership function thereof, wherein the membership function is quantified into a finite number of levels corresponding to a finite number of degrees of truth, and is stored as a characteristic value of each subset of fuzzy variable values being all mirrored in one value of said degree of membership corresponding to one of said levels. The computing method includes generating a binary sequence; generating an address signal from the bits in the binary sequence; reading the contents of the memory storing the membership functions at each address signal to obtain a characteristic value; and comparing the characteristic value with the value of a fuzzy input variable.

Abstract: A high-density plasma process is proposed for depositing a layer of Silicon Nitride on a substrate in a plasma reactor. The process includes the steps of: providing a gas including precursor components of the Silicon Nitride, generating a plasma applying a radio-frequency power to the gas, and the plasma reacting with the substrate to deposit the layer of Silicon Nitride. The power applied to the gas is in the range from 2.5 kW to 4 kW.

Abstract: A system for admission control in a wireless local area network adapted to serve a set of stations and manage real time transmission as well as and TCP/IP sessions includes an access point (AP) configured for: when either a new station joins the network or a new TCP/IP session is being initiated, checking if sufficient bandwidth is available in the network for the new traffic flow associated with the new station or TCP/IP session without interfering with any ongoing real time transmission in the network, and in case no sufficient bandwidth is found to be available, whereby said new traffic flow could interfere with said ongoing real time transmission, blocking such new traffic flow.

Abstract: A method for manufacturing a MOS transistor integrated into a chip of semi-conductive material comprising a first and a second active region which extend from the inside of the chip to a surface of the chip. The method comprises the steps of: a) forming a layer of insulating material on the surface of the chip and depositing a layer of conductive material on said insulating layer, b) defining an insulated gate electrode of the transistor, from said superimposed insulating and conductive layers, c) defining, from said superimposed insulating and conductive layers, an additional structure arranged on a first surface portion of the first active region, and d) placing between the insulated gate electrode and the additional structure a dielectric spacer placed on a second surface portion of the first active region.

Abstract: A digital logic system includes a reset input for receiving a reset signal, and a clock input for receiving an externally generated main clock signal. An ancillary clock generator generates an ancillary clock signal. A clock selection multiplexer has a first input for receiving the externally generated main clock signal, a second input for receiving the internally generated ancillary clock signal, and an output for providing the externally generated main clock signal or the internally generated ancillary clock signal to a functional circuit. A resettable edge-triggered shift register has a first input for receiving the externally generated main clock signal, a second input for receiving the reset signal, and an output connected to the clock selection multiplexer for deselecting the internally generated ancillary clock signal and selecting the externally generated main clock signal after detecting a certain number of edges of the main clock signal following the reset signal.

Abstract: A method for encoding and decoding media signals, includes the operations of generating at a transmitting side multiple descriptions associated to data of the media signals through a downsampling operation performed on the data, and decoding at a receiving side the multiple descriptions for reconstructing the data by merging the multiple descriptions. The operation of generating multiple descriptions further includes the operations of obtaining a spectral representation of the data, including bands associated to different ranges, the bands being obtained by a suitable quantization operation and including at least one highly quantized band, that is subjected to a higher degree of quantization. A scrambling operation is performed on the spectral representation by moving the at least one highly quantized band to a different range, the scrambling operation being performed prior the downsampling operation. In decoding, a descrambling operation is performed before the merging operation on the multiple descriptions.

Abstract: A process for fabricating high-voltage drain-extension transistors, whereby the transistors are integrated in a semiconductor substrate along with non-volatile memory cells that include floating gate transistors.

Abstract: A driving circuit of a DC motor includes a control circuit for providing a control signal, and a motor drive circuit commanded by the control circuit for providing respective command signals for the switches of an output power stage connected to the DC motor. The output power stage is connected to a power supply line and drives the windings of the DC motor. The driving circuit prevents generation of voltage surges having a significant magnitude on the power supply line because the driving circuit has logic circuits for preventing any substantial inversion in the direction of current flow in the supply lines when the DC motor operates as a current generator.

Abstract: A nonvolatile memory device with simultaneous read/write has a memory array formed by a plurality of cells organized into memory banks, and a plurality of first and second sense amplifiers. The device further has a plurality of R/W selectors associated to respective sets of cells and connecting the cells of the respective sets of cells alternately to the first sense amplifiers and to the second sense amplifiers.

Abstract: A data transceiving station of digital data frames includes a digital modem coupled to a transmission line, and a microprocessor receiving demodulated data from the modem according to a Packet Mode or a Bit Mode transmission through an interface circuit. The interface circuit switches between the Packet Mode and the Bit Mode transmission during transfer of a data frame to the microprocessor. The data transceiving station combines the superior speed of a Packet Mode transfer with the unlimited compatibility of a Bit Mode transfer.

Abstract: The memory device includes a plurality of memory chips of a certain capacity assembled in a single package and sharing input/output pins, the memories being selectable and singularly enabled one at the time by appropriate external commands coherently with the currently addressed memory location. The device uses only one external enable/disable logic command applied through a single dedicated pin. Each of the memory chips has a number of additional input/output pads equal to 2*n, where 2n is the number of memory chips contained in the device, and a dedicated circuit that generates an internal enable/disable command, as a function of logic inputs corresponding to the logic states of the additional pads and the external enable/disable command.

Abstract: Method for manufacturing a semiconductor pressure sensor, wherein, in a silicon substrate, trenches are dug and delimit walls; a closing layer is epitaxially grown, that closes the trenches at the top and forms a suspended membrane; a heat treatment is performed so as to cause migration of the silicon of the walls and to form a closed cavity underneath the suspended membrane; and structures are formed for transducing the deflection of the suspended membrane into electrical signals.

Abstract: A digital microphone device outputs a digital audio signal to a digital signal processing system. The digital microphone device includes an acoustic transducer for producing an analog voltage signal representative of an acoustic signal, and an integrated circuit including an input multiplexer. The input multiplexer has a first analog input coupled to an output of the acoustic transducer, and a second analog input to be connected to an output of a remote external analog microphone providing an analog voltage signal. A variable gain analog signal pre-amplifier is coupled to an output of the input multiplexer.

Abstract: The method for encoding and/or decoding video signals, includes the operations of generating at a transmitter side a multiple descriptions vector associated to a pixel values vector of the video signals and decoding at a receiver side available descriptions vector for reconstructing the pixel values vector. The operation of generating a multiple descriptions vector includes the steps of obtaining the pixel values vector by selecting a group of pixels in a picture of the video signal and applying an encoding matrix to the pixel values vector. The decoding operation includes the step of applying a decoding matrix that is in an inverse relationship with the encoding matrix to the available descriptions vector to obtain the pixel values vector.

Abstract: An AC differential amplifier includes a pair of identical differential transconductance stages. Each transconductance stage includes a pair of inputs and a pair of outputs. The pairs of output of the transconductance stages are connected in common, and form a pair of output nodes of the AC differential amplifier. The pair of output nodes is also connected to a supply line through respective load resistors. One input of one transconductance stage is coupled through a capacitive device to an input of the other transconductance stage. The other inputs of the transconductance stages form the input terminals of the AC differential amplifier.

Abstract: A device for the correction of the power factor in power supply units with forced switching operating in transition mode is described. The device comprises a converter and a control device coupled to said converter so as to obtain from an alternating network input voltage a regulated output voltage on the output terminal. The converter comprises a power transistor and the control device comprises a pilot circuit suitable for determining the period of switched-on time and the period of switched-off time of said power transistor and control means coupled to said pilot circuits and with said converter and which are capable of prolonging said period of switched-on time of the power transistor at the instants of time in which the alternating network voltage substantially assumes the value zero.

Abstract: The invention relates to a method for pinpointing erase-failed memory cells and to a relevant integrated non-volatile memory device, of the programmable and electrically erasable type comprising a sectored array of memory cells arranged in rows and columns, with at least one row-decoding circuit portion per sector being supplied positive and negative voltages. This method becomes operative upon a negative erase algorithm issue, and comprises the following steps: forcing the read condition of a sector that has not been completely erased; scanning the rows of said sector to check for the presence of a spurious current indicating a failed state; finding the failed row and electrically isolating it for re-addressing the same to a redundant row provided in the same sector.

Abstract: A vertical-current-flow resistive element includes a monolithic region having a first portion and a second portion arranged on top of one another and formed from a single material. The first portion has a first resistivity, and the second portion has a second resistivity, lower than the first resistivity. To this aim, a monolithic region with a uniform resistivity and a height greater than at least one of the other dimensions is first formed; then the resistivity of the first portion is increased by introducing, from the top, species that form a prevalently covalent bond with the conductive material of the monolithic region, so that the concentration of said species becomes higher in the first portion than in the second portion. Preferably, the conductive material is a binary or ternary alloy, chosen from among TiAl, TiSi, TiSi2, Ta, WSi, and the increase in resistivity is obtained by nitridation.

Abstract: A charge pump is proposed. The charge pump is integrated in a chip of semiconductor material and includes a plurality of capacitive elements each one connected to a corresponding circuit node of the charge pump, the circuit nodes being arranged in a sequence from an input node to an output node, a plurality of field effect transistors each one for selectively connecting a corresponding first circuit node with a second adjacent circuit node, each transistor being made in a corresponding insulated body region, and for each transistor first biasing means for equalizing the body region with the first circuit node when the transistor is closed, wherein for each transistor the charge pump further includes second biasing means for equalizing the body region with the second circuit node when the transistor is opened.

Abstract: The memory device has a memory block, formed by a plurality of standard sectors and a redundancy portion; a control circuit, which controls programming and erasing of the data of the memory cells; and a correctness verifying circuit for the data stored in the memory cells. The correctness verifying circuit is enabled by the control circuit and generates an incorrect-datum signal in the event of detection of at least one non-functioning cell. The control circuit moreover activates redundancy, enabling the redundancy portion and storing redundancy data in a redundancy-memory stage in response to detecting an incorrect datum. Various solutions implement column, row and sector redundancy, both in case of erasing and programming.