Abstract: A phase change memory device includes a plurality of phase-change memory cells, arranged in rows and columns, phase-change memory cells arranged on the same column being connected to a same bit line; a plurality of first selectors, each coupled to a respective phase-change memory cell; an addressing circuit for selectively addressing at least one of the bit lines, one of the first selectors, and the phase-change memory cell connected to the addressed bit line and to the addressed first selector; and a regulated voltage supply circuit, selectively connectable to the addressed bit line, for supplying a bit line voltage. The bit line voltage is correlated to a first control voltage on the addressed first selector, coupled to the addressed phase-change memory cell.

Abstract: A ferroelectric semiconductor memory includes an arrangement of memory units comprising at least one row of memory units. The memory units of the at least one row are associated with a respective word line of the arrangement. The arrangement of memory unit includes a plurality of local word lines branching off from the word line associated with the at least one row, each local word line being connected to a respective group of memory units of the line. Selective connection means allow to selectively connect one of the local word lines to the respective word line. The arrangement of memory units further includes a plurality of local plate biasing lines, each one associated with the memory units of a respective group of memory units, for selectively driving the memory units of the respective groups.

Abstract: A line selector for a matrix of memory elements, for example a word line selector, comprises a plurality of line group selection circuits, each one allowing the selection of a respective group of matrix lines according to an address; each matrix line group includes at least one matrix line. Flag means are associated with each line group, that can be set to declare a pending status of a prescribed operation, for example an erase operation, for the respective matrix line group. Means are provided for entrusting the flag means with the selection of the respective line group during the execution of the prescribed operation, in alternative to the respective line group selection circuit. The flag means enable, when set, the execution of the prescribed operation on the respective matrix line group.

Abstract: Integrated microreactor, formed in a monolithic body and including a semiconductor material region and an insulating layer; a buried channel extending in the semiconductor material region; a first and a second access trench extending in the semiconductor material region and in the insulating layer, and in communication with the buried channel; a first and a second reservoir formed on top of the insulating layer and in communication with the first and the second access trench; a suspended diaphragm formed by the insulating layer, laterally to the buried channel; and a detection electrode, supported by the suspended diaphragm, above the insulating layer, and inside the second reservoir.

Abstract: The phase change memory cell is formed by a resistive element and by a memory region of a phase change material. The resistive element has a first thin portion having a first sublithographic dimension in a first direction; and the memory region has a second thin portion having a second sublithographic dimension in a second direction which is transverse to said first direction. The first and second thin portions are in direct electrical contact and define a contact area having sublithographic extent. The second thin portion is formed in a slit of sublithographic dimensions. According to a first solution, oxide spacer portions are formed in a lithographic opening, delimited by a mold layer. According to a different solution, a sacrificial region is formed on top of a mold layer and is used for forming the sublithographic slit in the mold layer.

Abstract: An integrated gyroscope, including an acceleration sensor formed by: a driving assembly; a sensitive mass extending in at least one first and second directions and being moved by the driving assembly in the first direction; and by a capacitive sensing electrode, facing the sensitive mass. The acceleration sensor has an rotation axis parallel to the second direction, and the sensitive mass is sensitive to forces acting in a third direction perpendicular to the other directions. The capacitive sensing electrode is formed by a conductive material region extending underneath the sensitive mass and spaced therefrom by an air gap.

Abstract: The driving voltage of the motor is incremented a quantity proportional to the speed of the motor according to a proportionality factor that is adjusted to compensate the back electromotive force. A method includes open-loop voltage control of a DC motor having a certain design speed constant, through a driving signal that is determined for imparting a certain acceleration to the motor and by generating a driving voltage of an output power stage to which the winding of the motor is connected as a function of the driving signal.

Abstract: In a device that includes a pair of closed-loop voltage regulators each including an input transconductance stage receiving a reference voltage and a feedback voltage, an intermediate transresistance stage, an output buffer operatively in cascade for generating on an output node the regulated output voltage and negative feedback means for providing the feedback voltage to the input stage, the method includes a circuit that limits the difference between two output regulated voltages. The limiting circuit includes a differential transconductance amplifier input with voltages proportional to the output voltages of the regulators or obtained by adding an offset voltage to the output voltage of the regulators for injecting in, or draining from, an input node of the intermediate stage of one of the regulators, a current as a function of the relative unbalance of the differential transconductance amplifier.

Abstract: A memory device includes a multi-protocol interface having at least two interfaces. Each interface decodes a respective communication protocol when enabled by a respective interface enable signal. The memory device further includes an automatic selection circuit for selecting one of the interfaces corresponding to a received communication protocol. The automatic selection circuit compares bits transmitted during a preamble of a received communication protocol cycle with pre-established bit patterns corresponding to preambles of the communication protocols associated with the at least two interfaces, and generates an enable signal for one of the interfaces based upon the comparison.

Abstract: A variable charge pump contains several individual simple charge pumps, each with a pumping capacitor and a switching mechanism. Additionally, a switching network is coupled to the individual charge pumps so that the different lines in the charge pump can be connected together in a serial mode or parallel mode (or mixed serial and parallel modes) to match the needs of the output load. The switching network is easily changed to provide the necessary driving capability as the needs of the output load changes.

Abstract: A micromachined device made of semiconductor material is formed by: a semiconductor body; an intermediate layer set on top of the semiconductor body; and a substrate, set on top of the intermediate layer. A cavity extends in the intermediate layer and is delimited laterally by bottom fixed regions, at the top by the substrate, and at the bottom by the semiconductor body. The bottom fixed regions form fixed electrodes, which extend in the intermediate layer towards the inside of the cavity. An oscillating element is formed in the substrate above the cavity and is separated from top fixed regions through trenches, which extend throughout the thickness of the substrate. The oscillating element is formed by an oscillating platform set above the cavity, and by mobile electrodes, which extend towards the top fixed regions in a staggered way with respect to the fixed electrodes. The fixed electrodes and mobile electrodes are thus comb-fingered in plan view but formed on different levels.

Abstract: A method for decrypting the encrypted messages sent by a transmission device to a first electronic device associated with a first trusted authority and to a second electronic device (ME). In one embodiment, first and second tokens are generated and exchanged, respectively, by the first and second electronic devices, which then generate a joint decryption key in order to decrypt the encrypted message.

Abstract: The method of coding data within a data processing unit includes a representation as twos-complement and a coded representation of the data. The coded representation is a semi-negated representation. A data processing unit includes a memory device connected bidirectionally to a data bus, itself connected to a processing architecture which includes at least one arithmetic-logic unit. Advantageously, the data processing unit includes at least one data coding/decoding block connected between the processing architecture and the data bus.

Abstract: A method of designing and fabricating a control unit for electronic microcontrollers or microprocessors that includes fabricating a finite state machine having at least one combinatorial network, the finite state machine having a plurality of control subunits, each control subunit structured to correspond to one combinatorial logic network. Each unit in the plurality of control subunits is independently connected to an arbitration block to provide information about a possible future state and to receive a present state command.

Abstract: Described herein is a read/write transducer for a hard disk drivewith dual actuation stage, comprising at least one hard disk and at least one suspension carrying the read/write transducer. The read/write transducer comprises a supporting body having a substantially parallelepipedal shape, a read/write head arranged on a front face of the supporting body, and a grating defined on one of the side faces of the supporting body during the process of manufacture of the read/write transducer. The grating enables measurement of the position of the read/write transducer with respect to the corresponding suspension in an optical way using a laser transmitter emitting and directing towards the grating a laser beam, and a laser receiver arranged to intercept the laser beam reflected by the grating and outputting a position signal on the basis of which it is possible to calculate, in a simple way, the position of the read/write transducer with respect to the corresponding suspension.

Abstract: The invention relates to a virtual sensor of exhaust emissions from a fuel-injection endothermic engine having a combustion chamber in each of its cylinders, a fuel injector serving each combustion chamber, and an electronic fuel-injection control unit. Advantageously, the virtual sensor includes an input interface receiving a signal from at least one pressure sensor for measuring the pressure inside at least one combustion chamber of the engine, a second input interface receiving signals from the electronic fuel-injection control unit, and a calculation block to provide estimates of the amounts of nitrogen compounds and particulates in the emissions based on the pressure and other relevant signals to the engine operation.

Abstract: A process for encoding digital video signals organized in frames comprises the operations of dividing the frames into blocks starting from macroblocks subjected to motion-compensation and applying to the blocks a discrete cosine transform in such a way as to generate respective sets of coefficients. The sets of coefficients are then assembled by being organized into sets of vectors by a assembling module. Once the variance of the vectors has been detected, the vectors themselves are quantized on a number of available bits by a pyramid vector quantizer, associating to the vectors respective quantization pyramids having given sizes according to the variance detected and to the number of available bits. Finally, the vectors are encoded with respective codewords.

Abstract: A process for the fabrication of devices that integrate protected microstructures, comprising the following steps: forming, in a body of semiconductor material, at least one microstructure having at least one first portion and one second portion which are relatively mobile with respect to one another and are separated from one another by at least one gap region, which is accessible through a face of the body; and sealing the gap. The sealing step includes depositing on the face of the body a layer of protective material, in such a way as to close the gap region, the protective layer being such as to enable relative motion between the first portion and the second portion of the microstructure.

Abstract: A frequency/signal converter is provided that receives an input clock signal and generates an output signal. The converter includes a first circuit that receives the input clock signal and generates first and second logic signals that are complementary with one another, a loop circuit that includes a first circuit line and a second circuit line that are each coupled between a first supply voltage and a second supply voltage, and an integrator device. A current proportional to the output signal of the converter flows in the loop circuit. The first and second circuit lines include first and second capacitive elements and first and second switches for interrupting current flow into the first and second capacitive elements, respectively. The first and second switches are controlled by the first and second logic signals, respectively.

Abstract: A self-repair method intervenes at the end of an operation of modification of a nonvolatile memory, selected between programming and erasing, in the event of detection of just one non-functioning cell, and carries out redundancy of the non-functioning cell. To this end, the memory array is divided into a basic portion, formed by a plurality of memory cells storing basic data, and into an in-the-field redundancy portion. The in-the-field redundancy portion is designed to store redundancy data that include a correct content of the non-functioning cell, the address of the non-functioning cell, and an activated redundancy flag. The redundancy is activated only after applying a preset maximum number of modification pulses and uses a redundancy replacement circuit and a redundancy data verification circuit.