Abstract: The high-gain photodetector is formed in a semiconductor-material body which houses a PN junction and a sensitive region that is doped with rare earths, for example erbium. The PN junction forms an acceleration and gain region separate from the sensitive region. The PN junction is reverse-biased and generates an extensive depletion region accommodating the sensitive region. Thereby, the incident photon having a frequency equal to the absorption frequency of the used rare earth crosses the PN junction, which is transparent to light, can be captured by an erbium ion in the sensitive region, so as to generate a primary electron, which is accelerated towards the PN junction by the electric field present, and can, in turn, generate secondary electrons by impact, according to an avalanche process. Thereby, a single photon can give rise to a cascade of electrons, thus considerably increasing detection efficiency.

Abstract: The present invention relates to a particular single cell erasing method for recovering memory cells under reading or programming disturbs in non volatile semiconductor memory electronic devices comprising cell matrix split in sectors and organized in rows, or word lines, and columns, or bit lines. This kind of memory devices generally provides the application of a sector erasing algorithm with subsequent testing phase (erase-verify); but the method according to the present invention provides a bit by bit erasing by applying to each single word line a negative voltage used during the erasing of a whole sector and on the drain terminal of each single cell a programming voltage. With this kind of selective bias it is possible to perform a single cell, or bit by bit, erasing, allowing all the cells in case under a reading or programming disturb increasing the original threshold value thereof to be recovered.

Abstract: A switching power supply circuit is provided for capacitor charging, wherein a power device is coupled to a terminal node of a capacitor to be charged and has a control terminal coupled to the output of an associated drive circuit. This circuit includes a second power element being associated with the first power device, coupled to said terminal node, and provided with a control terminal which is connected directly to the output of respective drive logic. The second power element is driven to turn on when a voltage below a predetermined minimum is present at the capacitor, thereby pulling the voltage at the terminal node to ground and further charging the capacitor.

Abstract: The charge pump uses PMOS transistors for implementing the first and the second charge transfer switches of the charge pump. Substantially, the closing and opening of the first switch through which the first capacitor is charged, of the second switch for transferring the electric charge from the first capacitor to the load capacitance connected to the output node of the circuit and of the third switch for discharging to ground the load capacitance, are driven by a logic NOR gate. A first input of the NOR gate is connected to a common control node of the PMOS transistor forming the second switch and of a NMOS transistor forming the third switch, a second inverting input is connected to the output node, and the output is connected to the first capacitor.

Abstract: Digital signals are transmitted on a bus at given instants selectively in a non-encoded format and an encoded format so as to minimize the switching activity on the bus. Given the same value of switching activity, the decision whether to transmit the signals in non-encoded format or in encoded format is taken according to the choice of maintaining constant, without transitions, the value of the additional signal, which signals that encoding of the signals transmitted each time has taken place or has been omitted.

Abstract: A non-volatile CAM-type memory having a multiplicity of memory cells ordered into a matrix of rows and columns, a word line and a match line associated with every row of cells and a first and a second bit line associated with every column of cells. In order to speed up the search for a data item in the memory and to simplify the circuit structure of the memory, each row of cells is associated with a ground control line and a ground line and every cell also includes a first controlled electronic switch connected between a ground line and a match line associated with the row containing the cell and having a control terminal connected to a match node of the cell and a second controlled electronic switch connected between the match node of the cell and the ground line associated with the row containing the cell, and further having a control terminal connected to the ground control line associated with the row containing the cell.

Abstract: A time delay logic comprises a first stage with an inverter, a capacitor connected to the input terminal of the inverter, a constant current generator and an electronic switch controlled by an input pulse. The capacitor begins to charge at a predetermined edge of the input pulse and brings the input terminal of the inverter from a first voltage (ground) to the switching threshold voltage of the inverter, so that on the output terminal of the inverter there is obtained a pulse having an edge that, as referred to the predetermined edge of the input pulse, has a delay time that depends on the inverter threshold. The circuit comprises a second stage, coupled with the first, that is a dual circuit of the circuit of the first stage and has an inverter equal to the one of the first stage.

Abstract: A method of driving an electrical load having a complex electrical impedance, such as a voice-coil motor controlling the position of a read/write head in a data storage disk drive system, comprises providing a voltage-mode driver generating drive signals for the electrical load in response to drive commands. Compensated commands for the voltage-mode driver are generated filtering the drive commands, compensating for a phase shift between electrical quantities delivered to the electrical load. The voltage-mode drive thus emulates a conventional, but more expensive, current-mode drive. In a preferred embodiment, the method comprises estimating characteristic parameters of the electrical load during the operation, and adapting the filtering to the estimated characteristic parameters. The estimation comprises implementing a Kalman filtering algorithm, particularly an extended Kalman filtering.

Abstract: A non-volatile memory device suitable to be programmed in a sequential mode. The device includes a plurality of blocks of memory cells each one for storing a word, each block being identified by an address. An input circuit for loading an input address at the beginning of a programming procedure and an internal circuit for setting an internal address to the input address. The device further includes a data input circuit for loading a predetermined number of input words in succession, and a latch circuit for latching a page consisting of the predetermined number of input words. The memory then executes a programming operation including writing the page in the blocks identified by consecutive addresses starting from the internal address, and increments the internal address of the predetermined number in response to the completion of the programming operation.

Abstract: The circuit comprises a differential amplifier with two inputs and two outputs and a common mode regulation circuit. Between a regulation terminal of the amplifier and the outputs there are connected first and second capacitors and first and second capacitive elements that by controlled switches are connected in parallel with, respectively, the first and second capacitors or alternately between first and second reference voltage terminals. The common mode output voltage is not exactly fixed at the beginning of the design, but is determined by attributing appropriate values to the first and second capacitive elements; more particularly, their capacitances C3 and C4 are chosen in such a way as to satisfy the following equality: Vcmn=Vrefl+[(Vrefp?Vrefm)/2]*(C4?C3)/(C3+C4), where Vcmn is the desired common mode output voltage, Vrefp and Vrefm are the differential output voltages and Vrefl is the voltage of the second reference terminal.

Abstract: A method for determining an effective resistance of a voltage controlled DC motor having a nominal resistance includes driving the DC motor with a signal so that the DC motor has a targeted acceleration, and sensing an effective acceleration of the DC motor. The effective resistance of the DC motor is determined as a function of the nominal resistance, the targeted acceleration and the effective acceleration.

Abstract: A device for processing data to be interleaved and stored in target memories includes N interleaving buffers, N producers, and N cells. Each cell includes a register bank of size W, and a delay circuit. The variable M defines a maximum number of concurrent write operations supported per time step W, and defines a maximum buffer size. These parameters are chosen to reflect a standard case. At any time step, each of the N interleaving buffers receives m log-likelihood ratio (LLR) inputs and writes up to M of these into the register banks. When m is larger than M, m-M producers are delayed by the delay circuit. When a buffer overflow occurs (more than W LLRs values), m producers are delayed by the delay circuit. One LLR value is fetched from the register bank and is written in an SRAM interleaving memory.

Abstract: A geometric processing stage for a pipelined engine for processing video signals and generating processed video signal in space coordinates (S) adapted for display on a screen. The geometric processing stage includes: a model view module for generating projection coordinates of primitives of the video signals in a view space, said primitives including visible and non-visible primitives, a back face culling module arranged downstream of the model view module for at least partially eliminating the non visible primitives, a projection transform module for transforming the coordinates of the video signals from view space coordinates into normalized projection coordinates (P), and a perspective divide module for transforming the coordinates of the video signals from normalized projection (P) coordinates into screen space coordinates (S). The back face culling module is arranged downstream the projection transform module and operates on normalized projection (P) coordinates of said primitives.

Abstract: A memory device having a reading configuration and including a plurality of memory cells, arranged in rows and columns, memory cells arranged on the same column having respective first terminals connected to a same bit line and memory cells arranged on the same row having respective second terminals selectively connectable to a same word line; a supply line providing a supply voltage; a column addressing circuit and a row addressing circuit for respectively addressing a bit line and a word line corresponding to a memory cell selected for reading in the reading configuration. The column addressing circuit is configured to bias the addressed bit line corresponding to the selected memory cell substantially at the supply voltage in the reading configuration.

Abstract: A method for management of the programming controls in a multilevel device is provided. During the control step cells are not controlled all together but they are conveniently selected in order to reduce the source resistance and consumption effect, but without penalizing change times.

Abstract: A process for transmitting data on a bus, minimizing the switching activity, involves converting the data between a first format and a second format used for transmission of the data. The conversion between said first format and said second format entails the swapping of position of respective bits within a cluster comprising a given number of bits, the swap operation being implementable according to different variants, the maximum number of said variants being equal to the factorial of the aforesaid given number. Each of said variants is identified by a respective pattern. Among the aforesaid patterns, an optimal pattern is selected which minimizes the switching activity at the moment of transmission of data on the bus. The data are then transmitted on the bus using the second format generated using said optimal pattern.

Abstract: A device for decoding audio signals subjected to a noise-reduction encoding such as a Dolby-B encoding comprises a plurality of processing blocks (612, 616, 620, 624, 628, 632, 636, 640) for generating, starting from an input signal (610) containing the audio signal subjected to encoding superimposed on a noise component, an output signal (626) consisting of a replication of the audio signal with the noise component reduced. The aforesaid processing blocks are implemented in a digital form and comprise a sliding-band filtering structure (612) fed with the input signal (610) and designed to generate a filtered signal (614). The filtered signal (614) is fed, according to a general feedforward scheme, to an overshoot-suppression stage (616) in view of the generation, in an adder node (620), of a difference signal (622) starting from which the output signal is obtained via filtering (624).

Abstract: An LDMOS device includes elementary MOS cells. The gate structure of the elementary cell includes a first conductor material finger. The LDMOS device includes first metal stripes for contacting source regions, second metal stripes for contacting drain regions, and third metal stripes placed on inactive zones for contacting a material finger by forming a contact point. The contact point is formed by a first prolongation of the material finger for connecting with one of the third stripes. The third metal stripe includes at least one fourth metal stripe placed on a separation zone. The material finger has a second prolongation and the fourth metal stripe has a first prolongation to form an additional contact point.

Abstract: A method of producing an output bitstream of coded digital video data with a bit-rate different from the bit-rate of an input bitstream includes dividing the input bitstream into a sequence of coded data and a sequence of control bits. The sequence of control bits is modified as a function of the desired bit-rate of the output bitstream that is different from the bit-rate of the input bitstream. An output sequence of control bits is produced. The method further includes decoding the sequence of coded data producing an intermediate sequence of data, and quantizing with a pre-established step and coding the intermediate sequence of data producing an output sequence of coded data. The output sequences producing the output bitstream are merged with the desired bit-rate.

Abstract: The microreactor has a body of semiconductor material; a large area buried channel extending in the body and having walls; a coating layer of insulating material coating the walls of the channel; a diaphragm extending on top of the body and upwardly closing the channel. The diaphragm is formed by a semiconductor layer completely encircling mask portions of insulating material.