Abstract: A method establishes a communication between a first electronic device associated with a first trusted authority and a second electronic device. The method includes: making a first key available to the first device for the communication between the first authority and the first device. A second trusted authority, associated with the second device and distinct and autonomous with respect to the first authority, generates a second key in order to communicate with the second device. Furthermore, the method includes: making the second key available to the second device; and providing the first and second devices with a communication key, to be used communication between the first and second devices, through at least one of the first and second authorities.

Abstract: A method of processing a bitstream of coded data of video sequences of progressive or interlaced pictures includes estimating motion vectors of groups of pixels. These groups of pixels belong to a top half-frame of the current picture in relation to pixels belonging to a bottom half-frame of a preceding picture. Motion vectors are also estimated for group of pixels of a bottom half-frame of the current picture in relation to pixels belonging to the top half-frame of the current picture. The processing calculates for each macroblock of a top half-frame and a bottom half-frame a respective top motion coefficient and a bottom motion coefficient depending on the estimation of the motion vectors of the top half-frame and the bottom half-frame. The current picture is recognized as an interlaced picture by a substantial equality of the distributions of values of the motion coefficients, or as a progressive picture by a substantial inequality of the distributions of values of the motion coefficients.

Abstract: An integrated non-volatile memory device may include a first matrix of memory cells organized into rows (or word lines) and columns (or bit lines), corresponding row and column decoding circuits, and read, modify and erase circuits for reading and modifying data stored in the memory cells. Furthermore, the memory device may also include a test structure including a second matrix of memory cells smaller than the first. The second memory matrix may include word line couplings each having a different contact to gate distance. That is, each coupling is aligned a different distance from its respective gate than adjacent couplings.

Abstract: A method and device emulate the features of a EEPROM memory device. The device is included into a memory macrocell which is embedded into an integrated circuit comprising also a microcontroller. The device includes a Flash EEPROM memory structure formed by a predetermined number of sectors wherein at least two sectors of the Flash memory structure are used to emulate EEPROM byte alterability.

Abstract: A MOS device has: a semiconductor body defining a surface; a stack on top of the semiconductor body; and a passivation layer on top of the semiconductor body and covering the stack. The stack is formed by a first polysilicon region and by a second polysilicon region arranged on top of one another and separated by an intermediate dielectric region. An electrical connection region extends through the passivation layer as far as the surface of the semiconductor body laterally with respect to, and in contact with, the first and the second polysilicon regions so as to contact them electrically.

Abstract: The integrated structure and process is effective to form, in a dielectrically insulated well, a MOS component including respective drain and source regions of a first conductivity type as well as a gate region. The integrated structure includes a cut-off layer of the second conductivity type effective to surround only the source region. The cut-off layer is self-aligned by the gate region.

Abstract: The method for using a nonvolatile memory (1) having a plurality of cells (14), each of which stores a datum, is based upon the steps of performing an modification operation of erasing/programming (22) the data of the memory; verifying (23) the correctness of the data of the memory cells; and, if the step of verifying (23) has revealed at least one incorrect datum, correcting on-th-field (46) the incorrect datum, using an error correcting code. The verification (23) of the correctness of the data is performed by determining (23) the number of memory cells storing an incorrect datum; if the number of memory cells storing the incorrect datum is less than or equal to a threshold (46), the erroneous datum is corrected by the error correction code; otherwise, new erasing/programming pulses are supplied.

Abstract: A linear phase detector has a variable gain that is regulated as a function of the monitored transition density of the input signal. The transition density is sensed by a circuit that generates a signal corresponding to a time averaged common mode component of the differential signal output by an output stage of the phase detector.

Abstract: A phase detector receives an oscillating signal and a clock signal, and outputs a differential signal representing a phase difference therebetween. The phase detector includes a first differential pair of transistors respectively driven by the clock signal and by an inverted clock signal for generating the differential signal. An auxiliary differential pair of transistors is coupled to the first differential pair of transistors and is respectively driven by the oscillating signal and by an inverted oscillating signal. A current generator biases the first differential pair of transistors and the auxiliary differential pair of transistors.

Abstract: A modular information processing system is disclosed. The system includes an expansion device that embeds at least one internal peripheral without a controller and/or at least one port for connecting an external peripheral. The system further includes a hand-held computer that embeds control circuitry including at least one controller for the at least one internal peripheral or at least one external peripheral, and an interface for coupling the hand-held computer to the expansion device in a removable manner. In a mobile operating condition in which the hand-held computer is not coupled to the expansion device, the processing circuitry controls the hand-held computer. In an expanded operating condition in which the hand-held computer is coupled to the expansion device, the processing circuitry controls a personal computer formed by the hand-held computer and the expansion device. Also provided are a hand-held computer and an expansion device for use in modular information processing systems.

Abstract: An A/D converter having capacitors of a first array of sampling capacitors weighted in binary code connected between a first common circuit node and an input terminal to be charged to an input voltage with respect to a ground of a signal to be converted, and in accordance with SAR technique are then selectively connected with two differential reference terminals, and at the same time capacitors of a second array equal to the first and all connected to a second node are selectively connected to ground and the lower differential voltage terminal. The two nodes are connected to the respective inputs of a comparator. A logic unit controls the connections of the capacitors of the two arrays in accordance with a predetermined timing program and as a function of the output of the comparator.

Abstract: An architecture for distributing supply voltages to a plurality of memory modules supplied through a plurality of charge pump circuits may include a sorting block bi-directionally connected to the plurality of memory modules, from which it may receive a plurality of power requests. The sorting block may provide a sorting signal based upon a priority scale to drive the plurality of charge pump circuits and distribute supply voltages to the plurality of memory modules. The architecture may advantageously be software-configurable.

Abstract: A multiphase buck type voltage regulator having at least two phases and including a first switching means that selectively connect a supply voltage to a load through a first current path; a second switching means that selectively connect said supply voltage to said load through a second current path; a first activation circuit that activates said first switching means; a first delay circuit that deactivates said first switching means after a first period of time; a second activation circuit that activates said second switching means; a second delay circuit that after a second period of time deactivates said second switching means; said first period of time depends on said supply voltage and on the output voltage; said second period of time depends on said supply voltage and on a voltage proportional to the difference of current that flows in said first and second current path.

Abstract: An integrated device having a pad receiving, in a standard operative condition, an input signal having a first value and, in a test operative condition, a test voltage having a second value higher than the first value; an input stage connected to the pad and including an electronic component having a first terminal connected to the pad; a third-level detecting stage connected to the pad and supplying a logic third-level signal having a first level in presence of the input signal and a second level in presence of the test voltage; and a selector connected to a second terminal of the electronic component and structured to connect the second terminal to a reference potential in the presence of the first logic level of the third-level signal and to a biasing voltage higher than the reference potential and lower than the second value in the presence of the second logic level of the third-level signal.

Abstract: A sensing circuit for a memory cell includes a first bias current generator connected between a first voltage reference and a first inner circuit node, and a second reference current generator connected to the first voltage reference. A comparator having a first input terminal is connected to a comparison circuit node that is connected to the second reference current generator, a second input terminal is connected to a circuit node that is connected to the first inner circuit node, and an output terminal forms an output terminal of the sensing circuit. A cascode-configured bias circuit is connected between the inner circuit node and a matching circuit node. The cascode-configured bias circuit is also connected to a second voltage reference. A current/voltage conversion stage is connected to the matching circuit node, to the comparison circuit node, and to a third voltage reference.

Abstract: An encryption process includes choosing a secret key and a set of permutable functions defined on a phase space for encrypting/decrypting messages, choosing a code for encoding messages to be sent as a number belonging to the phase space. The set of permutable functions includes chaotic maps generated by a composite function of first and second functions, and an inverse of the first function. The secret key is defined by the second function.

Abstract: An architecture of a nonvolatile memory device, though not requiring dedicated pins and by introducing circuit modifications that require a negligible additional silicon area in the serial interface, allows a selection between at least two different serial communication protocols, thus multiplying the occasions of employment of the same device. The selection of one or of the another serial communication protocol is carried out by setting, during the testing on wafer (EWS) of the devices being fabricated, a certain UPROM cell of the array of UPROM cells that is normally present in a standard nonvolatile memory device for setting during the fabrication the characteristics of ATD, redundancy and other functions of the memory device. Alternatively, the customer can make the selection by placing an appropriate signal level on a specified pin of the memory device.

Abstract: A memory device includes a multi-protocol interface having at least two interfaces. Each interface decodes a respective communication protocol when enabled by a respective interface enable signal. The memory device further includes an automatic selection circuit for selecting one of the interfaces corresponding to a received communication protocol. The automatic selection circuit compares bits transmitted during a preamble of a received communication protocol cycle with pre-established bit patterns corresponding to preambles of the communication protocols associated with the at least two interfaces, and generates an enable signal for one of the interfaces based upon the comparison.

Abstract: A method of establishing an encrypted communication by means of keys between a first electronic device associated with a first trusted authority and a second electronic device, including generating a first secret key associated with the first device for the management of the communication, generating, at least in part by means of the first authority, a second secret key associated with the second device for the management of the communication. The method includes generating the first key at least in part by a second trusted authority associated with the second device that is distinct and autonomous from the first authority. Alternatively, the generation of the first key is performed, at least in part, by the second device passing through the second trusted authority.

Abstract: A memory device includes an array of memory cells organized into a plurality of sectors, and local wordlines and local bitlines are connected to the memory cells in each respective sector. Main read wordlines and main program wordlines are connected to the local wordlines in each sector. A main read row decoder is connected to the main read wordlines, and a main program row decoder connected to the main program wordlines. Main read bitlines and main program bitlines are connected to the local bitlines in each sector. A main read column decoder is connected to the main read bitlines, and a main program column decoder is connected to the main program wordlines. A read address bus is connected to the main read row decoder and to the main read column decoder for providing an address thereto. A program address bus is connected to the main read column decoder and to the main program row decoder for providing an address thereto.