Abstract: An electronic circuit structure for updating a block of memory cells in a flash memory device, the memory cells storing a current value, wherein the structure includes a data latch for receiving a new value to be written on the memory cells, a controller for erasing the block of memory cells simultaneously, and programming load bank coupled to the controller and the data latch for programming the memory cells individually; the structure further includes control logic coupled to the controller for enabling the controller and for enabling the programming load bank according to a comparison between the new value and the current value.

Abstract: A MOS semiconductor device formed on a substrate of a first conductivity type is provided. The device includes active zones for elementary active elements, and at least one inactive zone suitable for electric signal input or output. The substrate is connected with the drain terminal of the device, and at least one of the elementary active elements includes a body region of a second conductivity type that is connected with the source terminal of the device. The at least one inactive zone includes a semiconductor region of the second conductivity type formed in the substrate and adjacent a surface of the substrate, a conductive layer located over the semiconductor region, and a silicon oxide layer located between the semiconductor region and the conductive layer. The silicon oxide layer has alternating first zones and second zones that are contiguous to each other, with the first zones having a greater thickness than the second zones.

Abstract: A method for programming a non-volatile memory device of the multi-level type, includes a plurality of transistor cells grouped into memory words and conventionally provided with gate and drain terminals. The method applies different drain voltage values at different threshold values. Such values are directly proportional to the threshold levels to be attained by the individual memory word bits, and effective to provide for a simultaneous attainment of the levels, in a seeking-to manner, of the levels at the end of a limited number of pulses. Advantageously, a constant gate voltage value is concurrently applied to the gate terminals of said cells, such that the cell programming time is unrelated to the threshold level sought.

Abstract: A transconductance amplifier for inductive loads and a relevant inductive load driving method, the amplifier having an input stage receiving a driving signal (set-point), a power stage connected downstream of the input stage and connected to the load and an output stage fedback on the input stage to transfer a signal associated to the load. Advantageously, the input stage comprises at least a comparator receiving on one input the driving signal and on another input the output of the output stage. A delay block is also provided between the comparator output and the power stage to delay the comparator switching. This can be obtained also by using a hysteretic comparator.

Abstract: A bandgap voltage generator includes an output node for providing an output voltage, a current mirror coupled between the output node and a voltage reference, and a biasing transistor coupled to the output node. A feedback line includes a feedback transistor coupled to the output node. A current generator biases the feedback transistor by injecting a current into a bias node of the feedback line. A capacitor is coupled between the bias node and the voltage reference. The feedback line includes a circuit coupled between the bias node and the feedback transistor for causing a current to flow through the feedback transistor, and for increasing a resistance of a portion of the feedback line in parallel to the capacitor.

Abstract: A process forms a phase change memory cell using a resistive element and a memory region of a phase change material. The resistive element has a first thin portion having a first sublithographic dimension in a first direction; and the memory region has a second thin portion having a second sublithographic dimension in a second direction transverse to the first dimension. The first thin portion and the second thin portion are in direct electrical contact and define a contact area of sublithographic extension. The second thin portion is delimited laterally by oxide spacer portions surrounded by a mold layer which defines a lithographic opening. The spacer portions are formed after forming the lithographic opening, by a spacer formation technique.

Abstract: An interface manages the exchange of information between a bus system and a memory during reading, according to a communication protocol. The interface has a protocol-decoding unit, which receives from outside commands and information for managing the reading and generates a wait-code enabling signal, and a wait-state generating unit, which is connected to the protocol-decoding unit and outputs wait codes upon receipt of the wait-code enabling signal. When the memory ends reading, as signaled by switching of a read-state signal, a wait-state disabling circuit generates and supplies an end-of-waiting control signal to the wait-state generating unit, which thus outputs an end-of-waiting code.

Abstract: Management of Test Access Port functions of a plurality of components arranged on a single chip by selectively driving the TAP function of each of the components with respective clocks, whilst the further signals for driving the TAP function are used in a shared mode among the various components. Preferably, associated with the aforesaid clocks is a pull-down function for selectively blanking the respective clocks in conditions of non-use. In a preferred way, the aforesaid dedicated clocks are generated on board the chip.

Abstract: A digital system comprises a digital data processing unit, at least one output buffer connected to the processing unit to generate output signals in response to digital signals arriving from the processing unit and at least one user unit connect as output buffer load. With a view to assuring that the switching current of the output buffer can be set to different values, the output buffer comprises means for fixing the switching current to a value that is substantially constant and independent of the load and means for selectively setting the value of the switching current and the processing unit comprises means for storing a predetermined parameter; said means are connected to the selective setting means for setting the values of the switching current as functions of the predetermined parameter.

Abstract: A method for manufacturing a MOS transistor integrated into a chip of semi-conductive material comprising a first and a second active region which extend from the inside of the chip to a surface of the chip. The method comprises the steps of: a) forming a layer of insulating material on the surface of the chip and depositing a layer of conductive material on said insulating layer, b) defining an insulated gate electrode of the transistor, from said superimposed insulating and conductive layers, c) defining, from said superimposed insulating and conductive layers, an additional structure arranged on a first surface portion of the first active region, and d) placing between the insulated gate electrode and the additional structure a dielectric spacer placed on a second surface portion of the first active region.

Abstract: A voltage regulator with quick response includes: an output terminal supplying a regulated voltage; and at least a first boost circuit, controlled for alternately accumulating a first charge in a first operating condition and supplying the first charge to the output terminal in a second operating condition. In addition, the first boost circuit is provided with a compensation stage supplying the output terminal with a second charge substantially equal to the first charge, when the first boost circuit is in the first operating condition.

Abstract: A device converts a differential signal (Vin1, Vin2) to a single signal (Vout). The device includes at least one pair of transistors (Q1, Q2) having equal transconductance gain (gm) and arranged according a differential stage configuration. The transistors (Q1, Q2) have the differential signal (Vin1, Vin2) in input at the drivable terminals, have first non drivable terminals coupled respectively to first terminals of a first (R1) and a second (Rout) passive elements having second terminals connected with a first supply voltage (VDD), second non drivable terminals coupled to a second supply voltage (VEE) lower than the first supply voltage (VDD). The first terminal of the second passive element (Rout) is the output terminal (OUT) of the device.

Abstract: The present invention relates to leads of a No-Lead type package which includes a chip having an active surface and a rear surface opposite the active surface. The active surface has a plurality of connection points with a plurality of leads arranged around the perimeter of the chip and a first and a second surface orthogonal to said first surface. A plurality of connection wires connect electrically the bonding pads of the chip to the first surface of the leads respectively. The package also includes a welding compound suitable for encapsulating the chip, the first surface of the leads and the bonding pads. The leads possess at least one hole in the second surface of the leads.

Abstract: An integrated device based upon semiconductor technology, in particular a chemical microreactor, including a semiconductor body having a high-temperature operating portion and a low temperature operating portion. The semiconductor body is provided with a thermal-insulation device including a dissipator element arranged between the high-temperature operating portion and the low-temperature operating portion. The dissipator includes a membrane connecting the high-temperature operating portion and the low-temperature operating portion, and a plurality of diaphragms that extend substantially orthogonal to the membrane and are parallel to one another.

Abstract: A circuit device is provided for driving an AC electric load, of the type inserted between a terminal of an AC power supply line and a terminal of the electric load to be driven and including a generator of PWM signals to be transferred to the load. This circuit is an AC/AC converter adapted to power supply the load from any level of the power supply line sinusoid and comprising first and second voltage driven switches, the first switch to power supply the load and the second switch to enable loop-back of the current. The switches always operate in a complementary manner, i.e., when the first switch is on, the other is off, and vice versa.

Abstract: A method and circuit for accessing a memory location comprising at least one respective ferroelectric storage unit of a matrix of ferroelectric storage units, the memory location is selected by connecting a first terminal of a ferroelectric storage element of the at least one respective storage unit to a respective access line to the memory location; at least another memory location to which is not intended to be accessed is also selected. A second terminal of the ferroelectric storage element is biased to a prescribed access electric potential, and an electric potential on the access line is sensed; the second terminal of the ferroelectric storage elements of the other memory location is also biased to the access potential.

Abstract: A disk drive system is described which includes a disk having a magnetic surface and a motor for rotating the disk, a magnetic head being movable relative to said magnetic surface. The motor generates a back electromotive force voltage having different phases and the system comprising a plurality of switches for switching the back electromotive force voltage, a control circuit to control the plurality of switches to supply the back electromotive force voltage to direct the head to a parking position. The system also comprises a comparator adapted to compare a single phase of the back electromotive force voltage with the sum of the other phases of the back electromotive force voltage. The comparator generates an output signal representative of the comparation and the system comprises a logic block controlled by the output signal of the comparator. The logic block is adapted to determine time periods and a control sequence of the switches which is associated to the time periods.

Abstract: A method for associating with a digital image a class of a plurality of predefined classes having respective models, the method including the phases of dividing the digital image pixel by pixel into one or more regions belonging to a set of predefined regions that differ from each other on account of their type of content, the division being effected by establishing whether or not a pixel of the image belongs to a respective region on the basis of an operation of analyzing the parameters this pixel, the analysis operation being carried out by verifying that the parameters satisfy predefined conditions and/or logico-mathematical relationships of belonging to the respective region, acquiring from the digital image divided into regions information regarding the regions that are present in it, comparing this information with at least one model characterizing a respective class of said plurality, and associating with the digital image a class on the basis of the comparison phase.

Abstract: Sensing circuitry for reading and verifying the contents of electrically programmable and erasable non-volatile memory cells, comprises a sense amplifier having a first sensing circuit portion connected to a cell to be read and provided with an output terminal for connection to a first input terminal of a comparator, and having a second reference circuit portion connected to a reference current generator and provided with an output terminal for connection to a second input terminal of said comparator, characterized in that said first and said second circuit portions comprise a series of first and second transistors, respectively, being connected between a first voltage reference and a second voltage reference and having respective points of interconnection connected to said output terminals of said first and second circuit portions.

Abstract: An MOS electronic device is formed to reduce drain/gate capacity and to increase cutoff frequency. The device includes a field insulating layer that covers a drain region, delimits an active area with an opening, houses a body region in the active area, and houses a source region in the body region. A portion of the body region between drain and source regions forms a channel region. A polycrystalline silicon structure extends along the edge of the opening, partially on the field insulating and active layers. The polycrystalline silicon structure includes a gate region extending along a first portion of the edge on the channel region and partially surrounding the source region and a non-operative region extending along a second portion of the edge, electrically insulated and at a distance from the gate region.