Abstract: The phase change memory cell is formed by a resistive element and by a memory region of a phase change material. The resistive element has a first thin portion having a first sublithographic dimension in a first direction; and the memory region has a second thin portion having a second sublithographic dimension in a second direction transverse to the first dimension. The first thin portion and the second thin portion are in direct electrical contact and define a contact area of sublithographic extension. The second thin portion is delimited laterally by oxide spacer portions surrounded by a mold layer which defines a lithographic opening. The spacer portions are formed after forming the lithographic opening, by a spacer formation technique.

Abstract: A method of fabricating a MOS transistor with a controllable and modulatable conduction path through a dielectric gate oxide is disclosed, wherein the transistor structure comprises a dielectric oxide layer formed between two silicon plates, and wherein the silicon plates overhang the oxide layer all around to define an undercut having a substantially rectangular cross-sectional shape. The method comprises the steps of: chemically altering the surfaces of the silicon plates to have different functional groups provided in the undercut from those in the remainder of the surfaces; and selectively reacting the functional groups provided in the undercut with an organic molecule having a reversibly reducible center and a molecular length substantially equal to the width of the undercut, thereby to establish a covalent bond to each end of the organic molecule.

Abstract: A nonvolatile memory device is operable in a serial mode and in a parallel mode. The architecture of the nonvolatile memory device is based upon the structure already present in a standard memory, but includes certain modifications. These modifications include the addition of a timing state machine for the various memory access phases (i.e., writing and reading data), and the addition of an internal bus and related logic circuits for disabling the internal address bus of the standard memory when the nonvolatile memory device operates in the serial mode.

Abstract: A motion estimation process in video signals organized in successive frames divided into macroblocks that is carried out by the identification of motion vectors. In a first identification phase, starting from a current motion vector, a best motion vector predictor is identified, chosen from a set of candidates. The best predictor thus identified is then subjected to a second refining phase. The aforesaid set of candidates is identified by selecting vectors belonging to macroblocks close to the current vector within the current frame and the preceding frame. Preferably, the refining phase comprises the definition of a grid of n points centered on the central position to which the best motion vector points and the distance of the points of the grid from the center is defined as a function of the matching error typically consisting of an SAD function, defined in the first identification phase. Application to the IPB and APM operating modes of the H.263+ video standard is envisaged.

Abstract: A protection structure against electrostatic discharges for a semiconductor electronic device that is integrated inside a well is disclosed, wherein the well is formed on a SOI substrate and isolated dielectrically by a buried oxide layer and an isolation structure, which isolation structure includes in turn at least a dielectric trench filled with a filler material. Advantageously, the protection structure is formed at the isolation structure.

Abstract: For encoded membership functions used to identify atomic conditions defining antecedents of fuzzy inferences, and also for determining operands of the antecedents, corresponding stores are configured to store already available values of these encoded membership functions and of the operands. At the time of identification of a new value for the quantities, a check is made to see whether this value is already present in the corresponding store. If the outcome of this check is positive for encoded membership functions, pointers by which the encoded fuzzy inferences point to these functions is changed, so that the pointers are redirected towards the membership functions which are already stored. For operands of the antecedents, the check of the corresponding back-up store is carried out preferably based on the corresponding calculation values, the calculation of a new operand being disabled when the corresponding calculation parameters are already present in the corresponding back-up store.

Abstract: A packaging structure for optoelectronic components is formed by a first body, of semiconductor material, and a second body, of semiconductor material, fixed to a first face of said first body. A through window is formed in the second body and exposes a portion of the first face of the first body, whereon at least one optoelectronic component is fixed. Through connection regions extend through the first body and are in electrical contact with the optoelectronic component. The through connection regions are insulated from the rest of the first body via through insulation regions. Contact regions are arranged on the bottom face of the first body and are connected to said optoelectronic component via the through connection regions.

Abstract: A metal oxide semiconductor transistor integrated in a wafer of semiconductor material includes a gate structure located on a surface of the wafer and includes a gate oxide layer. The gate oxide layer includes a first portion having a first thickness and a second portion having a second thickness differing from the first thickness.

Abstract: A dielectric insulation structure is formed in a silicon layer by integrating a dielectric trench structure therein. The dielectric trench structure defines an insulation well where semiconductor devices are to be integrated therein. The dielectric trench structure is on a hollow region that is completely surrounded by a dielectric area. The dielectric area also forms the side insulation of the dielectric trench structure. The dielectric trench structure is interrupted by a plurality of points to define a plurality of side support regions for the insulation well.

Abstract: A method for determining switching sequences of two-dimensional unary arrays of conducting branches of thermometrically decoded D/A converters, in a way that will ensure that the relative INL error function be contained between pre-established symmetrical upper and lower bound functions, has been found. When these upper and lower bound functions are constant, the obtained switching sequence compensates both the linear and the quadratic component of the error distribution and therefore is affected by a very small absolute INL error, which depends essentially on the random component of the error distribution. This method may be easily implemented by a computer program and allows the realization of thermometrically decoded D/A converters affected by a known limited INL error function.

Abstract: A process for forming a final passivation layer over an integrated circuit comprises a step of forming, over a surface of the integrated circuit, a protective film by means of High-Density Plasma Chemical Vapor Deposition.

Abstract: A process for forming a trench gate power MOS transistor includes forming an epitaxial layer having a first type of conductivity on a semiconductor substrate, and forming a body region having a second type of conductivity on the epitaxial layer. A gate trench is formed in the body region and in the epitaxial layer. The process further includes countersinking upper portions of the gate trench, and forming a gate dielectric layer on surfaces of the gate trench including the upper portions thereof. A gate conducting layer is formed on surfaces of the gate dielectric layer for defining a gate electrode. The gate conducting layer has a thickness that is insufficient for completely filling the gate trench so that a residual cavity remains therein. The residual cavity is filled with a filler layer. The gate conducting layer is removed from an upper surface of the body region while using the filler layer as a self-aligned mask. The edge surfaces of the gate conducting layer are oxidized.

Abstract: An architecture for a pipeline processor circuit, preferably of the VLIW type, comprises a plurality of stages and a network of forwarding paths which connect pairs of said stages, as well as a register file for operand write-back. An optimization-of-power-consumption function is provided via inhibition of writing and subsequent readings in said register file of operands retrievable from said forwarding network on account of their reduced liveness length.

Abstract: A method manufactures a single electron transistor device by electro-migration of nanocluster wherein said nanoclusters are metallically passivated and forced to assembly over a lithographic patterned substrate under control of a non homogeneous electric field at room temperature. A controlled migration and the desired location of the metallic passivated nanoclusters are based on a dielectrophoretic process.

Abstract: A semiconductor substrate integrated electronic circuit includes a transmitter block and a receiver block connected through a communication network (4). A data signal having a transmission period is generated on a first line that is received by the receiver block. A congestion signal is generated on a second line from the receiver block to the transmitter block when a congestion event of the receiver block occurs in order to interrupt the data signal transmission. A synchro signal is generated on a third line starting from the transmitter block, this synchro signal indicating to the receiver block that the data signal comprises a new datum. The congestion signal also interrupts the synchro signal transmission when a congestion event of the receiver block occurs.

Abstract: A push-pull converter has a transformer provided with a primary winding and a secondary winding. A capacitive element is connected between the input terminals of the primary winding, and two switch elements are arranged between a respective input terminal of the primary winding through an inductor and a supply input of the converter. The current-input terminals of the switch elements are connected to one another, and the current-output terminals of the switch elements are each connected to the respective input terminals of the primary winding. The switch elements are made up of NPN bipolar transistors connected in common-collector configuration. The push-pull converter is particularly suited for driving a cold-cathode fluorescent lamp.

Abstract: A method of sensing a ferroelectric non-volatile information storage unit comprising two ferroelectric storage capacitors in mutually opposite polarization states, and a sensing circuit for actuating the method.

Abstract: A multi-output switching power supply may include a PWM regulator circuit arranged in cascade upstream of each output to receive, as an input, a square wave voltage signal with a predetermined duty cycle. The regulator circuit may include an auxiliary switching device for modulating the duty cycle of the input signal to supply, as an output, a regulated direct current voltage. A control circuit for the PWM regulator circuit may include a detector circuit for detecting the trailing edges of the voltage signal input to the regulator circuit which emits a pulse coinciding with each of the trailing edges. The control circuit may also include a ramp signal generator that is controlled by the emitted pulses. The ramp signal generator may be connected to the non-inverting input of a comparator having an inverting input for receiving a signal indicative of the error in the regulator output voltage.

Abstract: A circuit architecture and a method perform a page programming in non-volatile memory electronic devices equipped with a memory cell matrix and an SPI serial communication interface, as well as circuit portions associated to the cell matrix and responsible for the addressing, decoding, reading, writing and erasing of the memory cell content. Advantageously, a buffer memory bank is provided to store and output data during the page programming in the pseudo-serial mode through the interface. Data latching is performed one bit at a time and the following outputting occurs instead with at least two bytes at a time.

Abstract: A driving device is provided for driving at least one power transistor of a voltage converter that includes a piezoelectric transformer. The power transistor has a first non-drivable terminal coupled to an input voltage and to the input of the piezoelectric transformer. The converter includes an inductor coupled between the input voltage and the piezoelectric transformer, and a resistor coupled between a second non-drivable terminal of the power transistor and ground. The driving device is coupled to the drivable terminal of the power transistor, to the input of the piezoelectric transformer, and to the second non-drivable terminal of the power transistor so as to detect a first voltage value and a second current value. The driving device is adapted to cause the turning on of the power transistor if the first voltage value is equal to a third prefixed voltage value, and to cause the turning off of the power transistor if the second current value is equal to a fourth prefixed current value.