Abstract: A method is for forming a plastic protective package for an electronic device integrated on a semiconductor and comprising an electronic circuit to be encapsulated in the protective package. The electronic device may be at least partially activated from outside of the protective package. The method may include providing a mold having a half-mold with an insert abutting towards the inside of the mold and an end having an element that can be elastically deformed to abut in pressing contact against at least one portion of the integrated circuit. The method may also include injecting a resin into the mold so that the protective package has a hole by the at least one portion of the electronic circuit.

Abstract: An electrically-programmable memory cell programmed by means of injection of channel hot electrons into a charge-storage element capacitively coupled to a memory cell channel for modulating a conductivity thereof depending on a stored amount of charge. A first and a second spaced-apart electrode regions are formed in a semiconductor layer and define a channel region there between; at least one of the first and second electrode regions acts as a programming electrode of the memory cell. A control electrode is capacitively coupled to the charge-storage element. The charge-storage element is placed over the channel to substantially extend from the first to the second electrode regions, and is separated from the channel region by a dielectric layer. The dielectric layer has a reduced thickness in a portion thereof near the at least one programming electrode.

Abstract: An adjustable frequency oscillator circuit includes: an odd number of inverters connected so as to form a loop; a plurality of capacitive elements each connected to an output terminal of a respective inverter; and an output terminal, which supplies a signal oscillating at an oscillating frequency. The oscillator circuit further includes a calibration circuit for calibrating maximum currents which can be delivered by the inverters to the respective capacitive elements.

Abstract: A contact structure for a ferroelectric memory device integrated in a semiconductor substrate and includes an appropriate control circuitry and a matrix array of ferroelectric memory cells, wherein each cell includes a MOS device connected to a ferroelectric capacitor. The MOS device has first and second conduction terminals and is covered with an insulating layer. The ferroelectric capacitor has a lower plate formed on the insulating layer above the first conduction terminals and connected electrically to the first conduction terminals, which lower plate is covered with a layer of a ferroelectric material and coupled capacitively to an upper plate. Advantageously, the contact structure comprises a plurality of plugs filled with a non-conductive material between the first conduction terminals and the ferroelectric capacitor, and comprises a plurality of plugs filled with a conductive material and coupled to the second conduction terminals or the control circuitry.

Abstract: A DC—DC converter may comprise a plurality of voltage multiplying stages of the capacitive type, each multiplying stage comprising a plurality of selectively connectable boosting branches. In one embodiment, the DC—DC converter comprises an inductor connected between a supply line and a ground line through a switching transistor; a voltage multiplying circuit formed by a plurality of voltage multiplying stages of capacitive type, connected together in cascade and each having an input connected to an intermediate node between the inductor and the transistor, and an output supplying a potential equal to the potential of the intermediate node multiplied by a respective multiplication factor. Each voltage multiplying stage comprises a plurality of parallel, selectively connectable boosting branches. The number of the active boosting branches may be varied in response to the energy required by the loads.

Abstract: A differential non-volatile memory device is provided that includes setting means, at least first and second OTP memory cells that are each coupled between a supply voltage and a reference voltage, and a read circuit forming a first current path between the first memory cell and the reference voltage and a second current path between the second memory cell and the reference voltage for reading the bit and the complementary bit that are stored in the first and second memory cells. The first current path includes a first circuit point that is associated with a first output terminal, and the second current path includes a second circuit point that is associated with a second output terminal. The setting means can be activated to bring the first and second circuit points to a voltage value that is substantially equal to the reference voltage, and is able to set the value of the current flowing through each of the first and second current paths.

Abstract: An electrically erasable and programmable memory cell is provided. The memory cell includes a floating gate MOS transistor and a bipolar transistor for injecting an electric charge into the floating gate. The floating gate transistor has a source region and a drain region formed in a first well with a channel defined between the drain and source regions, a control gate region, and a floating gate extending over the channel and the control gate region. The bipolar transistor has an emitter region formed in the first well, a base region consisting of the first well, and a collector region consisting of the channel. The memory cell includes a second well that is insulated from the first well, and the control gate region is formed in the second well. Further embodiments of the present invention provide a memory including at least one such memory cell, an electronic device including such a memory, and methods of integrating a memory cell and erasing a memory cell.

Abstract: A method for controlling programming voltage levels of non-volatile memory cells comprises: providing a resistive divider connected to a programming voltage reference and effective to generate at least one programming voltage level; and providing a reference cell crossed by a cell current. Advantageously according to an embodiment of the invention the cell current is applied to the resistive divider to correlate the programming voltage level to the intrinsic features of the reference cell. A programming voltage regulator of non-volatile memory cells comprises at least an input stage inserted between a first and a second voltage reference and connected to a reference memory cell, as well as, in correspondence with its output terminal, to a resistive divider, inserted in turn between a programming voltage reference and the second voltage reference and connected to at least an output terminal of the regulator, effective to supply the programming voltage to the non-volatile memory cells.

Abstract: A disk drive may include a housing, and a rotatable data storage disk and associated disk drive motor carried by the housing for rotating the rotatable data storage disk. The disk drive may also include a movable arm and associated arm drive motor carried by the housing for moving the arm adjacent to the rotatable data storage disk. Further, at least one read/write head may be carried by the arm, and a driving circuit may be included for the arm drive motor. The driving circuit may include at least one output stage connected to a power supply for driving the arm drive motor, at least one capacitor connected to the power supply, and an auxiliary pulse width modulation (PWM) control circuit connected to the at least one capacitor for driving the at least one output stage in a PWM mode after the power supply is switched off.

Abstract: A subscriber's telephone system is presented that includes at least one driver circuit connected to Tip and Ring terminals. An additional network is connected between an output of the driver circuit and the Ring terminal. This additional network includes a suitably dimensioned capacitor and a diode limiter connected in parallel with each other to minimize the overall voltage while maintaining a desired battery mean value.

Abstract: An integrated circuit includes an input pad for receiving an externally generated analog signal, and a pre-sampling circuit for pre-sampling at least one internally generated analog reference signal. An analog-to-digital converter is connected to the input pad for providing a numerical value of the externally generated analog signal, and is connected to the pre-sampling circuit for providing a numerical value of the internally generated analog reference signal. A fault signaling circuit is connected to the pre-sampling circuit and to the analog-to-digital converter for generating a fault signal when the numerical value of the externally generated analog signal is equal to the numerical value of the internally generated analog reference signal. The fault signal indicates that an electrical connection providing the externally generated analog signal to the input pad is faulty.

Abstract: The cells of the stacked type each comprise a MOS transistor formed in an active region of a substrate of semiconductor material and a capacitor formed above the active region; each MOS transistor has a first and a second conductive region and a control electrode and each capacitor has a first and a second plate separated by a dielectric region material, for example, ferroelectric one. The first conductive region of each MOS transistor is connected to the first plate of a respective capacitor, the second conductive region of each MOS transistor is connected to a respective bit line, the control electrode of each MOS transistor is connected to a respective word line, the second plate of each capacitor is connected to a respective plate line. The plate lines run perpendicular to the bit line and parallel to the word lines. At least two cells adjacent in a parallel direction to the bit lines share the same dielectric region material and the same plate line.

Abstract: A voltage regulator includes an input terminal adapted for being coupled to an input voltage and an output terminal adapted for being coupled to a load. The voltage regulator includes a first switch adapted for selectively coupling to the input terminal and to the output terminal, a current sensor for measuring an output current flowing towards the output terminal, a voltage sensor for measuring the output voltage from the output terminal, and a digital controller which drives the first switch. The controller closes the first switch when the error voltage is less than a first preset value of voltage and opens the first switch when the output current is greater than a first preset value of current.

Abstract: The present invention proposes a Field Programmable Gate Array device comprising a plurality of configurable electrical connections, a plurality of controlled switches, each one adapted to activating/de-activating at least one respective electrical connection in response to a switch control signal and a control unit including an arrangement of a plurality of control cells. Each control cells controls at least one of said controlled switches by the respective switch control signal, each control cell including a volatile storage element adapted to storing in a volatile way a control logic value corresponding to a preselected status of the at least one controlled switch, and providing to the controlled switch said switch control signal corresponding to the stored logic value. Each control cell further includes a non-volatile storage element coupled to the volatile storage element, the non-volatile storage element being adapted to storing in a non-volatile way the control logic value.

Abstract: In a method for multiplication of floating-point real numbers, encoded in a binary way in sign, exponent and mantissa, the multiplication of the mantissa envisages a step of calculation of partial products, which are constituted by a set of addenda corresponding to the mantissa. In order to reduce the size and power consumption of the circuits designed for calculation, there is adopted a method of binary encoding which envisages setting the first bit of the mantissa to a value 1, in order to obtain a mantissa having a value comprised between 0.5 and 1. Also proposed are methods for rounding of the product and circuits for the implementation of the multiplication method. Also illustrated are circuits for conversion from and to encoding of floating-point teal numbers according to the IEEE754 standard. Preferential application is in portable and/or wireless electronic devices, such as mobile telephones and PDAs, with low power-consumption requirements.

Abstract: The system carries out conversion of digital video signals organized in blocks of pixels from a first format to a second format. The second format is a format compressed via vector quantization. The vector quantization is performed by means of repeated application of a scalar quantizer to the pixels of said blocks with a quantization step (Q) determined in an adaptive way according to the characteristics of sharpness and/or brightness of the pixels and representing said vector quantization in a n-dimensional space indicative of the characteristics on n of said pixels in the block partitioned into cells of size proportional to said quantization step, each cell being assigned to an appropriate binary code, wherein said process further includes identifying at least one symmetry element in said n-dimensional space suitable for separating at least two symmetrical set of cells, and selecting one of said at least two symmetrical set of cells for the assignment of said binary codes.

Abstract: Described herein is an erase method for an electrically erasable nonvolatile memory device, in particular an EEPROM-FLASH nonvolatile memory device, comprising a memory array formed by a plurality of memory cells arranged in rows and columns and grouped in sectors each formed by a plurality of subsectors, which are in turn formed by one or more rows. Erase of the memory array is performed by sectors and for each sector envisages applying an erase pulse to the gate terminals of all the memory cells of the sector, verifying erase of the memory cells of each subsector, and applying a further erase pulse to the gate terminals of the memory cells of only the subsectors that are not completely erased.

Abstract: A process for manufacturing a semiconductor wafer integrating electronic devices and a structure for electromagnetic decoupling are disclosed. The method includes providing a wafer of semiconductor material having a substrate; forming a plurality of first mutually adjacent trenches, open on a first face of the wafer, which have a depth and a width and define walls); by thermal oxidation, completely oxidizing the walls and filling at least partially the first trenches, so as to form an insulating structure of dielectric material; and removing one portion of the substrate comprised between the insulating structure and a second face of the wafer, opposite to the first face of the wafer.

Abstract: A step gain-variable CMOS amplifier includes an input pair of transistors, a bias current generator connected between a common source node of the input pair of transistors and a ground node, and a pair of load transistors. The pair of load transistors is connected between a supply voltage node and, respectively, to the drain nodes of the input pair of transistors. The CMOS amplifier includes a plurality of second input pairs of transistors to be connected in parallel to the input pair of transistors for increasing the effective width of the resultant transistors. Alternativelty, the CMOS amplifier includes a plurality of second load pairs of transistors to be connected in parallel to the load pair of transistors for increasing the effective width of the resultant transistors. Pairs of path selection switches may be programmably closed for connecting in parallel the selected pairs of transistors.

Abstract: A manufacturing method for a power device integrated on a semiconductor substrate with double thickness of a gate dielectric layer is described, which comprises the following steps: forming first dielectric portions having a first thickness; forming on the whole semiconductor substrate a first dielectric layer thinner than the first dielectric portions; forming a conductive layer on the first dielectric layer; forming a second dielectric layer on the conductive layer; performing an etching step of the second dielectric layer and of the conductive layer to form first spacers and a gate electrode, to define, between the gate electrode and the substrate, second dielectric portions in the first dielectric layer, the second dielectric portions being auto-aligned with the first portions.