Abstract: An integrated electronic circuit includes a plurality of active circuits connected together in cascade. A feedback loop is between an output of a last active circuit and an input of a first active circuit so that the plurality of active devices function as a non-linear device, such as an inductor. The integrated electronic circuit may be integrated or used in association with a circuit network including other non-linear devices.

Abstract: A chaotic signal generator includes a set of elements connected together for generating chaotic signals. The connection scheme may correspond to the circuit generally referred to as Chua's circuit, particularly when implemented as a cellular neural network. Interposed in the connection scheme is at least one switch, such as a MOS transistor. Opening and closing of the switch causes variation in the chaotic dynamics of the generated signals. A command signal applied to the switch may correspond to a modulating signal for transmission on a channel, such as a high noise channel. The modulating signal may be a binary signal, and the command signal may be a switching signal having a frequency that increases or decreases depending on the logic level of the binary signal.

Abstract: An integrated device comprising a MOS transistor and a Schottky diode which are formed on a semiconductor substrate of a first conductivity type is shown. The device comprises a plurality of body region stripes of a second conductivity type which are adjacent and parallel to each other, a first metal layer placed over said substrate and a second metal layer placed under said substrate. The device comprises a plurality of elementary structures parallel to each other each one of which comprises first zones provided with a silicon oxide layer placed over a portion of the substrate which is comprised between two adjacent body region stripes, a polysilicon layer superimposed to the silicon oxide layer, a dielectric layer placed over and around the polysilicon layer. Some body region stripes comprise source regions of the first conductivity type which are placed adjacent to the first zones of the elementary structures to form elementary cells of said MOS transistor.

Abstract: A method for detecting the position of a rotor of a DC motor with N phases having a plurality of windings, comprising the steps of connecting two of the windings between first and second prefixed voltages through to a first current path for a prefixed time, allowing the current stored in the two windings to discharge through a second current path; comparing the voltage across one of the two windings with a reference voltage and providing a control signal when the voltage is smaller in absolute value than the reference voltage, performing the above steps for each of the winding pairs of the motor; detecting the position of the rotor on the basis of the control signals obtained.

Abstract: A process for manufacturing an integrated device comprises the steps of: forming, in a first wafer of semiconductor material, integrated structures including semiconductor regions and isolation regions; forming, on a second wafer of semiconductor material, interconnection structures of a metal material including plug elements having at least one bonding region of a metal material capable of reacting with the semiconductor regions of the first wafer; and bonding the first and second wafers together by causing the bonding regions of the plug elements to react directly with the semiconductor regions so as to form a metal silicide. Thereby, the metallurgical operations for forming the interconnection structures are completely independent of the operations required for processing silicon, so that there is no interference whatsoever between the two sets of operations.

Abstract: To execute the cell-search procedure in a cellular communication system (such as a system based upon the 3GPP TDD standard), there are available identification codes for the second step (slot synchronization) and for the third step (identification of the scrambling codes). The identification codes are identified by a process of correlation with the received signal and are used for obtaining from a correspondence table the parameters for the execution of the second step (CD) or of the third step (SCR). The correspondence table is stored in a reduced form by the identification, according to rules of symmetry and redundancy, of subtables designed to generate the entire table by appropriate combination operations. The search procedure in the correspondence table thus reduced is conveniently modified by the introduction of the combination operations. A preferential application is in mobile communication systems based upon standards such as UMTS, CDMA2000, IS95 or WBCDMA.

Abstract: A process for manufacturing a phase change memory cell, comprising the steps of: forming a resistive element; forming a delimiting structure having an aperture over the resistive element; forming a memory portion of a phase change material in the aperture, the resistive element and the memory portion being in direct electrical contact and defining a contact area of sublithographic extension. The step of forming a memory portion further includes filling the aperture with the phase change material and removing from the delimiting structure an exceeding portion of the phase change material exceeding the aperture.

Abstract: An application-specific embeddable flash memory having three content-specific I/O ports and delivering a peak read throughput of 1.2 GB/s. The memory is combined with a special automatic programming gate voltage ramp generator circuit having a programming rate of 1 Mbyte/s for non-volatile storage of code, data, and embedded FPGA bit stream configurations. The test chip uses a NOR-type 0.18 ?m flash embedded technology with 1.8V power supply, two poly, six metal and memory cell size of 0.35 ?m2.

Abstract: A phase-locked loop circuit provides an output signal having a frequency depending on the frequency of a reference signal. The circuit includes a feedback circuit that derives a feedback signal from the output signal, a phase frequency detector that provides a control signal indicative of a phase difference between the reference signal and the feedback signal, a control circuit that controls the frequency of the output signal according to the control signal, and a conditioning circuit that conditions the control signal through a conditioning signal. The conditioning circuit includes a storage circuit that stores energy provided by the control signal and the conditioning signal during a first phase and transfers the accumulated energy to the control circuit during a second phase.

Abstract: An electrically-modifiable, non-volatile, semiconductor memory comprising a plurality of user memory locations which can be addressed individually from outside the memory in order to read and to modify the data held therein is characterized in that, for each user memory location, there is a corresponding pair of physical memory locations in the memory, which assume, alternatively, the functions of an active memory location and of a non-active memory location, the active memory location containing a previously-written datum and the non-active memory location being available for the writing of a new datum to replace the previously-written datum, so that, upon a request to replace the previous datum with the new datum, the previous datum is kept in the memory until the new datum has been written.

Abstract: The process for manufacturing a through insulated interconnection is performed by forming, in a body of semiconductor material, a trench extending from the front (of the body for a thickness portion thereof; filling the trench with dielectric material; thinning the body starting from the rear until the trench, so as to form an insulated region surrounded by dielectric material; and forming a conductive region extending inside said insulated region between the front and the rear of the body and having a higher conductivity than the first body. The conductive region includes a metal region extending in an opening formed inside the insulated region or of a heavily doped semiconductor region, made prior to filling of the trench.

Abstract: A method compresses a digital image including a matrix of elements each one including a plurality of digital components of different type representing a pixel. The method includes the steps of providing an incomplete digital image wherein at least one component is missing in each element, obtaining the digital image from the incomplete digital image, splitting the digital image into a plurality of blocks and calculating, for each block, a group of DCT coefficients for the components of each type, and quantizing the DCT coefficients of each group using a corresponding quantization table scaled by a gain factor for achieving a target compression factor. The method further comprises the steps of determining an energy measure of the incomplete digital image and estimating the gain factor as a function of the energy measure, the function being determined experimentally according to the target compression factor.

Abstract: A leadframe for semiconductor devices, including a region which is adapted to support a semiconductor device and a plurality of leads which are arranged so as to be directed toward the region, for mutual connection, by connecting wires connecting the leads and the semiconductor device. The leads include leads having at least two different lengths for the connection of connecting wires having different diameters.

Abstract: A device for measuring the relative angular position of two bodies with respect to a point is provided with a first measuring element and a second measuring element, relatively movable with respect to one another and connectable to a first body and a second body, respectively; the first measuring element includes a first inclination sensor, which has a first detection axis and supplies a first inclination signal, correlated to a first angle of inclination of the first detection axis with respect to a reference axis, and the second measuring element includes a second inclination sensor, which has a second detection axis and supplies a second inclination signal, correlated to a second angle of inclination of the second detection axis with respect to the reference axis.

Abstract: Integrated circuit including a power component with vertical current flow and at least one low or medium voltage component, the at least one low or medium voltage component formed in a first semiconductor layer separated from a second semiconductor layer by an insulating material layer. The power component with vertical current flow is formed in the second semiconductor layer, and excavations are formed in the insulating material layer which extend from a free surface of the first semiconductor layer to the second semiconductor layer, said excavations having lateral walls of insulating material and being filled up with a conductor material in order to electrically contact active regions of the power component in the second semiconductor layer by electrodes placed on the free surface of the first semiconductor layer.

Abstract: A voltage booster device to selectively assume an active status and a stand-by status with a first terminal to assume a respective electric potential and associated to a first capacitor, a second terminal associated to a second capacitor and selectively connectable to the first terminal, and a discharge circuit for discharging the first capacitor thus reducing the electrical potential of the first terminal, the discharge circuit being activated when said device is in the stand-by status and the second terminal is disconnected from said first terminal.

Abstract: A method for manufacturing a micro-electro-mechanical device, which has supporting parts and operative parts, includes providing a first semiconductor wafer, having a first layer of semiconductor material and a second layer of semiconductor material arranged on top of the first layer, forming first supporting parts and first operative parts of the device in the second layer, forming temporary anchors in the first layer, and bonding the first wafer to a second wafer, with the second layer facing the second wafer. After bonding the first wafer and the second wafer together, second supporting parts and second operative parts of said device are formed in the first layer. The temporary anchors are removed from the first layer to free the operative parts formed therein.

Abstract: Presented is a method for decoding-decompressing a compressed-encoded digital data sequence relating to at least one initial digital image. The method includes receiving the digital data sequence having compressed-encoded data groups separated from one another by at least one restart marker and each one including a respective set of encoded data structures. The method calculates a representative value of the number of encoded data structures being between a first restart marker and a subsequent second restart marker signalling, respectively, the start of a first data group to be decoded and the start of a second data group. The method then extracts from the first data group the encoded data structures, and detects the presence of at least one error, if the number of the encoded data structures extracted is different from the calculated value.

Abstract: A loop-type voltage regulating device, particularly for regulating a voltage of an automotive electric system that includes at least one thermal engine, a voltage regulator and an alternator operative to deliver a system regulated-voltage signal to and receive a regulation signal from the voltage regulator, the voltage regulating device including a control unit within the regulating loop, which unit is connected between the thermal engine and the voltage regulator and is adapted to supply the latter with a signal related to the engine operation.

Abstract: The invention relates to a process for manufacturing a light sensor device in a standard CMOS process, including at least the following phases: implanting active areas on a semiconductor substrate to obtain at least a first, a second and a third integrated region of corresponding photosensors; forming a stack of layers of different thickness and refractive index layers over the photosensors to provide an interferential filter for said photosensors. The stack is obtained by a deposition of a first oxide stack including a first, a second and a third oxide layer over at least one photosensor; moreover, this third oxide layer is obtained by a deposition step of an protecting undoped premetal dielectric layer.