Abstract: A circuit for receiving digital data arriving in series comprising a circuit for generating a reference dock and a circuit for oversampling the received data memorizing the samples sampled at the rate of several clocks phase-shifted with respect to the reference clock, the oversampling circuit comprising means for selecting and providing as output data samples representative of the received data and, further, a detection circuit identifying the variations of the phase shift between the reference clock edges and the transitions of the received data by analyzing the memorized samples, the detection circuit controlling a frequency variation of the reference dock when the phase shift variations repeat over several sampling cycles.

Abstract: An architecture of an ignition and/or injection managing system for an internal combustion engine, of the type structured to cooperate with an electronic engine control unit. Also included is an electronic device architecture for determining the operating phase of an internal combustion motor, of the type structured for cooperating with an electronic motor control unit and inputting a signal issued from a sensor of a phonic wheel associated with the motor camshaft. This device has the task of computing the operating phase by analyzing the signal from the sensor of the driving shaft phonic wheel, so as to release the electronic motor control unit from monitoring the phonic wheel signal, in order to lighten its computational load, and to enable the processing of the signal issuing from a variety of the phonic wheels more commonly used in the automotive industry.

Abstract: A method for manufacturing a semiconductor substrate of a first concentration type is described, which comprises at least a buried insulating cavity, comprising the following steps:

Abstract: An output buffer includes an output stage formed by a pull-up transistor and a pull-down transistor connected in series between a supply line set at a supply potential and a ground line set at a ground potential. The output buffer further includes a pre-biasing stage for pre-biasing the control terminal of the pull-up transistor and a pre-biasing stage for pre-biasing the control terminal of the pull-down transistor in order to bring these transistors to the turning-on threshold.

Abstract: A circuit for driving capacitive loads in a highly efficient manner. In one embodiment, a drive portion is connected to at least one end of a capacitive electric load being applied a voltage waveform. The embodiment further comprises a switching circuit portion having its output connected to the above one end of the capacitive load in order to supply a fraction of the overall current demanded by the load. Additionally, a switching circuit and accompanying switching method provide for efficiently supplying peak current to the capacitive load during voltage fluctuation in the voltage waveform. Briefly, the invention is a circuit arrangement aimed at providing a highly efficient drive for the capacitive load, using a combined linear/switching setup and without distorting the quality of the waveform generated across the capacitive load.

Abstract: An integrated structure formed on a semiconductor chip includes a substrate having a first conductivity type and an epitaxial layer grown on the substrate. The epitaxial layer may have the first conductivity type and also a conductivity less than a conductivity of the substrate. Moreover, the integrated structure may include a first region and a second region in the epitaxial layer, each having a conductivity type opposite that of the epitaxial layer. The first and second regions may extend from a surface of the epitaxial layer opposite the substrate into the epitaxial layer to form respective first and second junctions therewith. Further, the integrated structure may also include an isolating element for reducing an injection of current through the epitaxial layer from the first region to the second region when the first junction is directly biased.

Abstract: A method of estimating the motion field of a digital picture sequence includes subdividing a current picture to examine in an integer number of macroblocks, for each macroblock of the current picture determining a search window centered on a macroblock of a preceding picture placed in the same position of the considered macroblock of the current picture, carrying out a motion estimation between the considered macroblock of the current picture and the macroblock most similar to it included in the window. At least a dimension of the search window is established as a function of the corresponding dimension of the search window used for the preceding picture, the estimated motion field of the preceding picture and certain threshold values.

Abstract: A semiconductor device for electro-optic applications includes a rare-earth ions doped P/N junction integrated on a semiconductor substrate. The semiconductor device may be used to obtain laser action in silicon. The rare-earth ions are in a depletion layer of the doped P/N junction, and are for providing a coherent light source cooperating with a waveguide defined by the doped P/N junction. The doped P/N junction may be the base-collector region of a bipolar transistor, and is reverse biased so that the rare-earth ions provide the coherent light.

Abstract: A power supply circuit structure is useful with a row decoder for reading/writing data from/into memory cells of an integrated electrically programmable/erasable non-volatile memory device incorporating an array of multilevel memory cells. Advantageously, multiple supply voltages to the row decoder and a switching circuit for transferring the voltages over hierarchic-mode enabled conduction paths are provided.

Abstract: A device for detecting the pressure exerted at different points of a flexible and/or pliable object that may assume different shapes, includes a plurality of capacitive pressure sensors and at least a system for biasing and reading the capacitance of the sensors. The requirements of flexibility or pliability are satisfied by capacitive pressure sensors formed by two orthogonal sets of parallel or substantially parallel electrodes spaced, at least at each crossing between an electrode of one set and an electrode of the other set, by an elastically compressible dielectric, forming an array of pressure sensing pixel capacitors. The system for biasing and reading the capacitance includes column plate electrode selection circuits and row plate electrode selection circuits and a logic circuit for sequentially scanning the pixel capacitors and outputting pixel values of the pressure for reconstructing a distribution map of the pressure over the area of the array.

Abstract: A circuit device generates a signal proportional to the current circulating in an inductor and a current comparator, which is disabled by a stand-by signal, and is input with a feedback signal and with a signal proportional to the current circulating in the inductor and generates a logic comparison signal. A control logic, input with a logic comparison signal and the stand-by signal, drives the switch or the switches of a power stage. A clamp, connected in parallel to a capacitive branch, makes the feedback signal greater than a certain minimum threshold, to make the current that is delivered to the load, when the regulator is not in the stand-by state, greater than a certain minimum current.

Abstract: A process for manufacturing a dual charge storage location electrically programmable memory cell that includes the steps of forming a central insulated gate over a semiconductor substrate; forming physically separated charge-confining layers stack portions of a dielectric-charge trapping material-dielectric layers stack at the sides of the central gate, the charge trapping material layer in each charge-confining layers stack portion forming a charge storage element; forming side control gates over each of the charge-confining layers stack portions; forming memory cell source/drain regions laterally to the side control gates; and electrically connecting the side control gates to the central gate. Each of the charge-confining layers stack portions at the sides of the central gate is formed with an “L” shape, with a base charge-confining layers stack portion lying on the substrate surface and an upright charge-confining layers stack portion lying against a respective side of the insulated gate.

Abstract: A digital circuit for detecting a phase lock condition of a phase locked loop (PLL) circuit includes a pair of counters respectively receiving a digital signal produced by the PLL circuit, and a digital reference signal that is also received by the PLL circuit. A digital comparator is connected to the pair of counters for comparing count values contained therein at an end of a counting cycle, and for generating a first logic signal when the count values are the same and a second logic signal when the count values are different. A resettable memory receives the logic signals generated by the digital comparator and has a capacity sufficient to store a plurality of the logic signals resulting from successive comparisons.

Abstract: An NROM memory device, wherein the memory cells are provided with charge storage regions of insulating material, such as silicon nitride. The memory device includes a row decoder comprising a plurality of drivers; during programming, a first driver supplies a first voltage having a first value to a selected wordline, while the other drivers are configured so as to supply a second voltage having a second non-zero value, lower than the first value, to the other wordlines. Thereby, the gate-drain voltage drop of the deselected cells is reduced, and thus spurious erasing of the deselected cells connected to the selected bitline is reduced. Consequently, the reliability of the memory device is improved considerably and the life thereof is lengthened, thanks to the reduction in the charge injected into the charge storage region.

Abstract: A nonvolatile switch has: an input terminal; an output terminal; a selection terminal; a first and a second biasing terminal; a memory element of flash type, having a first conduction region connected to the first biasing terminal and a second conduction region connected to the second biasing terminal; a pass transistor, having a first conduction region connected to the input terminal and a second conduction region connected to the output terminal; and a common floating gate region and a common control gate region, which are capacitively coupled together. The memory element and the pass transistor share the common-gate regions, and the common control gate region is connected to the selection terminal.

Abstract: The invention relates to a voltage regulation system for multiword programming in non volatile memories, for example of the Flash type, with low circuit area occupation, wherein memories comprise at least a memory cell matrix organized in cell rows and columns and with corresponding circuits responsible for addressing, decoding, reading, writing and erasing the memory cell content. The memory cells have drain terminals connected to matrix columns and are biased in the programming step with a predetermined voltage value by means of program load circuits associated to each matrix column. In parallel with each program load circuit, a conduction-to-ground path is enabled by a controlled active element.

Abstract: A phase difference detector adapted to generating a signal indicative of a phase difference between a first signal and a second signal, comprising: a first bistable element clocked by the first signal and having a first output signal, and a second bistable element clocked by the second signal and having a second output signal; means for determining the variation of the signal indicative of the phase difference, responsive to the first and second output signals, and a reset circuit having a first and a second inputs respectively connected to the first and second output signals and adapted to determine the resetting of the first and second bistable elements in response to the attainment of a respective prescribed state by the first and the second output signals. The first and second inputs of the reset circuit are substantially symmetrical to each other from the point of view of an input impedance associated to each of them.

Abstract: A plurality of non volatile memory cells, for example of the flash type, with low circuit area occupation, are organized in cell matrices with corresponding circuits responsible for addressing, decoding, reading, writing and erasing the memory cell content. Each of the cells has a gate terminal biased in the programming phase with a predetermined voltage value through operation of charge pump voltage regulators. A first and a second regulation stage, which are structurally independent, are responsible for the programming and soft programming phase respectively. The first stage generates a supply voltage for the second stage.

Abstract: A fractional-type phase-locked loop circuit, for synthesising an output signal multiplying a frequency of a reference signal by a selected fractional conversion factor, includes a frequency divider for generating a feedback signal dividing the frequency of the output signal by a frequency division factor selectable among at least two different integer-value division factors, and frequency divider control means for causing the frequency division factor to vary between the at least two integer-value division factors in a pre-defined number of cycles, thereby an average frequency division factor over said pre-defined number of cycles has a fractional value. Means are provided for compensating a phase error introduced by the frequency divider on the basis of a value indicative of the phase error obtained from said frequency divider control means.

Abstract: A digital-to-analog converter includes a first section (MSB) that converts the more significant bits of a digital code into a first voltage (Vin) of a multiplicity of discrete voltages that are integral multiples of a predetermined first voltage step (&Dgr;V1). A second section (LSB) of the converter converts the less significant bits of the digital code into a current. The current is transformed into a second voltage of a multiplicity of discrete voltages that are integral multiples of a second voltage step (&Dgr;V2) equal to ½L of the product of the first voltage step (&Dgr;V1) multiplied by a predetermined coefficient, where L is the number of the less significant bits of the digital code to be converted. A summer generates an output voltage (Vout) that is the sum of the second voltage and the product of the first voltage multiplied by the predetermined coefficient. With a view to obtaining a low consumption, the summer has a resistive feedback circuit including a voltage divider (R3, R4).