Abstract: A memory device generator for generating memory devices in a CAD environment, the generator composed of a library file containing predefined basic circuit components; memory array generation algorithm interacting with the library file for generating a variable-size memory array representation having a variable number of memory elements, and at least one redundant memory element; memory element selection circuit generation algorithm interacting with the library file for generating a memory element selection circuit to be associated with the memory array for selecting at least one memory element according to memory device address inputs.

Abstract: A memory device includes an array of memory cells organized into a plurality of sectors, and local wordlines and local bitlines are connected to the memory cells in each respective sector. Main read wordlines and main program wordlines are connected to the local wordlines in each sector. A main read row decoder is connected to the main read wordlines, and a main program row decoder connected to the main program wordlines. Main read bitlines and main program bitlines are connected to the local bitlines in each sector. A main read column decoder is connected to the main read bitlines, and a main program column decoder is connected to the main program wordlines. A read address bus is connected to the main read row decoder and to the main read column decoder for providing an address thereto. A program address bus is connected to the main read column decoder and to the main program row decoder for providing an address thereto.

Abstract: A system for detecting distances for vehicle and robotic applications includes a transducer for generating a transmission signal to be sent in the direction of an obstacle, and for obtaining a receiving signal corresponding to an echo produced by the reflection of the transmission signal off the obstacle. The transducer is driven by a chaos generator, such as a Chua's circuit. The system also includes a correlator for correlating the transmission signal and the receiving signal so that the distance between the obstacle and the transducer is identified by an instant at which the correlation assumes a high value. The transmission signal may be a square-wave signal selectively generated with one first frequency and one second frequency, and jumps between the two frequencies are determined by the instants of emission of the pulses generated by an analog type pulse generator driven by the chaos generator.

Abstract: A method for encapsulating an electronic device is provided. The electronic device includes an integrated circuit, a lead frame for supporting the integrated circuit and having peripheral leads integrally formed therewith, and a heat sink thermally coupled to the lead frame. The heat sink includes an extension extending therefrom in a direction towards a corner of the electronic device. The method includes positioning the electronic device within a mold that includes a gate therein that is adjacent to and parallel with the extension. Molten insulative material is injected through the gate and into the mold for encapsulating the integrated circuit, and at least a portion of the lead frame and the heat sink.

Abstract: A method and a circuit for minimizing glitches in phase-locked loops is presented. The circuit includes an input terminal connected to an input of a phase detector; a series of a charge pump generator, a filter and a voltage controlled oscillator connected downstream of the phase detector; and a frequency divider feedback connected between an output of the voltage controlled oscillator and a second input of the phase detector. The circuit provides for the inclusion of a compensation circuit connected between the charge pump generator and the filter to absorb an amount of the charge passed therethrough. This compensation circuit includes a storage element connected in series to two switches. The first switch is coupled to and controlled by an output of the charge pump and the second switch is coupled to and controlled by an output of a phase detector.

Abstract: A protective envelope, made of a plastics material for enclosing a semiconductor integrated circuit, includes a flattened parallelepiped body having a sidewall formed of first and second portions set to converge toward each other. The envelope also includes a lead frame embedded in the body and bearing the integrated circuit, the lead frame having a section bent to form a baffle plate orientated toward the first sidewall portion. Advantageously, the bent section of the lead frame has a plane end edge extending parallel to the first sidewall portion at a spacing therefrom.

Abstract: A method is provided for driving a load in a pulse width modulation (PWM) mode as a function of numeric command values having a predetermined number of N-bits. The method includes the step of incrementing by more than a unit the number of bits on which a selected command value is mapped, wherein a unit equals N-bits plus a plurality of additional bits. The N most significant bits of the selected command value are converted. The plurality of additional bits are decoded by generating a corresponding plurality of intermediate levels of variation in the duty cycle. Each intermediate level has a duration of half a clock period and produces a plurality of signals out of phase among each other by half a clock period. A driving PWM signal is generated by multiplexing the signals out of phase among each other by half a clock period, and carrying out logic combinations of these signals as a function of a most significant bit of the selected command value and as a function of the plurality of additional bits.

Abstract: A voltage follower includes a follower stage including first and second bipolar junction transistors connected in cascade, and a first current generator connected to the follower stage for biasing the first and second bipolar junction transistors. A cascode stage is connected between the first current generator and the first bipolar junction transistor, and a second current generator is connected between the first bipolar junction transistor and a first voltage reference. The voltage follower dissipates less power when the output current is small.

Abstract: A memory system includes a memory matrix formed on a semiconductor structure. The memory matrix includes a first column line and a second column line which are connected electrically to at least one first memory cell to be read. For the reading of the at least one first cell, a first reading voltage can be supplied to the first column line. The memory matrix also includes a third column line distinct from the first column line and from the second column line. The memory matrix further includes generating circuit for supplying, to the third column line and during the reading of the at least one first memory cell, a biasing voltage which can oppose the establishment of an electric current between the first column line and the third column line in the semiconductor structure. The biasing voltage is preferably substantially equal to the first reading voltage.

Abstract: A digital input PWM power amplifier includes an oversampling and noise shaping circuit receiving pulse code modulated (PCM) digital input data organized in words of a first number of M bits at a bit rate, and outputting PCM digital data organized in words of a smaller number of N bits at a multiple bit rate. A first bus transmits a first number of most significant bits (MSB) of the N bit words output from the oversampling and noise shaping circuit, and a second bus transmits a second number of least significant bits (LSB) of the N bit words output from the oversampling and noise shaping circuit. First and second PCM/PWM converters are respectively fed with the first and second number of bits transmitted through the first and second buses. The PWM signal output by the first converter is summed to an attenuated PWM signal output by the second converter on the inverting input node of the output power stage.

Abstract: An effective organization and transferring of data among the functional blocks of an integrated system of a read channel of data recorded on DVD-Rom, DVD-Ram, DVD-R or CD Rom for performing Reed-Solomon decoding including off-line heroic correction, or deinterleaving, Reed-Solomon decoding is provided. The integrated system includes an input buffer, an interface with a microcontroller bus, a Reed-Solomon decoder, an embedded RAM accessed through a 17-bit bus, a descrambling and EDC control block for DVD modes of operation, a descrambling block for CD codes of operations, a data output interface, and a timing control block. The system permits the de coding of the input data acquired through the input buffer at a rate of up to four-times the reference bit rate of DVD formatted data using a clock for accessing the embedded RAM having a frequency half that of the clock that is used in the Reed-Solomon decoder, while reducing the number of accesses to the embedded RAM needed to perform the decoding.

Abstract: An electronic circuit is for the gradual start-up of electric loads, particularly halogen lamps. The circuit may include a power device having an output terminal connected to the electric load and having at least one control terminal receiving a predetermined driving current value. The circuit may further include a comparator having a first input terminal coupled to the power device output and a second input terminal kept at a reference potential. The comparator output may be connected to a controlled switch inserted upstream of the control terminal to control the opening of the switch and adjust the start-up phase of the power device according to the value of the reference potential.

Abstract: A mold for packaging an integrated semiconductor device includes two half shells closing on a perimeter dam bar of a die-stamped assembly metal frame of a semiconductor die that is between the two half shells of the mold. A depressed central pad of the metal frame defines, at least along an injection zone of the resin, a slit between the perimeter portion of the metal frame and the central pad. Resin flows through an inlet channel of the mold and through the slit to fill the upper and lower cavities. An edge of the central pad defining the slit is bent upward to form a spoiler intercepting the resin stream so that part of the resin is directed toward the lower cavity. The inner edge of the upper half shell of the mold defining the internal cavity along the injection side of the resin is inwardly offset.

Abstract: A circuit architecture and a method for performing a trimming operation directly on an application board, or after the operation of packaging integrated electronic devices. The circuit architecture includes at least one non-volatile memory unit (3) having non-volatile memory elements (5) and a circuit (17, 19) for modifying the state of the memory elements (5), a first multifunctional input pin (8) whereon a sequence (25) of trimming data is received, a second multifunctional input pin (9) whereon a timing signal of the trimming operations is received, and an additional access pin (7) for switching the circuit architecture operation from a normal mode over to a trimming mode.

Abstract: A method of forming metal connection elements in integrated circuits formed on adjacent areas of a wafer includes forming a conductive seed layer on a substrate of the wafer. A first mask covers the integrated circuits and leaves exposed areas of the seed layer overlying predetermined scribe lines used for separation of the integrated circuits. Using the seed layer as a cathode, a metal is deposited by an electrochemical process on exposed areas of the seed layer. The first mask is removed and a second mask is formed, leaving predetermined areas of the seed layer exposed. Using the seed layer as a cathode a metal is deposited on the exposed predetermined areas by an electrochemical process. The second mask is then removed. Connection elements of uniform thickness throughout the substrate are produced with the use of a very thin seed layer.

Abstract: A structure for a semiconductor resistive element, applicable in particular to power components, having a high concentration substrate of the n type, a first epitaxial layer of the n type, a region of the p type arranged on said first epitaxial layer so to form the resistive element proper, a second epitaxial layer of n type grown on said first epitaxial layer to make the region of the p type a buried region, and an additional layer of the n type with a higher concentration with respect to the second epitaxial level, positioned on the embedded region. Low resistivity regions of the p type adapted to make low resistivity deep contacts for the resistor are provided. The buried region can be made either with a development that is substantially uniform in its main direction of extension or so to present, at on part of its length, a structure of adjacent subregions in marginal continuity.

Abstract: An interface is provided for an integrated system that includes internal circuits, with each internal circuit functioning based upon its own clock. The interface includes a finite state machine for managing asynchronous and independent interactions between the internal circuits and external circuits. The finite state machine functions based upon a unique clock and a unique reset. The interface also includes an arbitration circuit connected to the finite state machine for receiving input signals for the finite state machine. The arbitration circuit includes a memory buffer for storing signals generated by the internal circuits when the finite state machine is performing an evaluation. The interface may be used to form a command interpreter of a non-volatile memory device.

Abstract: A device for detecting load impedance having an analog circuit portion for detecting the impedance value of a load, and a digital circuit portion adapted to provide load impedance type information. The analog circuit portion having two power MOS transistors connected in series to each other and between a supply voltage and the ground, and a pair of mirror MOS transistors common-connected with their respective gate terminals to the gate terminals of the power MOS transistors. The digital circuit portion includes a first comparitor to determine whether the output current of an audio amplifier is higher or lower than a threshold value and a second comparitor to determine whether the output voltage of the amplifier is higher than a threshold voltage, a memory to store output signals of the first and second comparitors, and a logic circuit arranged in cascade with the memory to output a load-type indication signal.

Abstract: An analog input circuit may include a pair of differential transconductance input stages having input nodes connected in parallel and which are fed the analog input signal. One of the differential transconductance stages may have common mode compatibility toward the supply node at the highest potential, and the other stage may have common mode compatibility toward the supply node at the lowest potential. Furthermore, differential output currents of the transconductance input stages may be summed differentially on first and second input nodes of a differential converter stage, which converts the differential current signals to an amplified differential voltage output signal.

Abstract: Method for fabricating integrated circuits comprising non-volatile memory cell matrices and peripheral circuits, said method comprising the steps of preparing a silicon substrate, carrying out a shallow trench isolation process on the silicon substrate to form active areas of exposed silicon isolated from one another by trenches filled with field oxide, growing a thin oxide layer on the active areas, masking the substrate areas intended for the memory cell matrices and etching the thin oxide layer and the field oxide by a chemical etch for a time longer than the time needed for removing the thin oxide layer entirely from the substrate areas intended for the peripheral circuits.