Abstract: The method is intended for manufacturing a microintegrated structure, typically a microactuator for a hard-disk drive unit and includes the steps of: forming interconnection regions in a substrate of semiconductor material; forming a monocrystalline epitaxial region; forming lower sinker regions in the monocrystalline epitaxial region and in direct contact with the interconnection regions; forming insulating material regions on a structure portion of the monocrystalline epitaxial region; growing a pseudo-epitaxial region formed by a polycrystalline portion above the structure portion of the monocrystalline epitaxial region and elsewhere a monocrystalline portion; and forming upper sinker regions in the polycrystalline portion of the pseudo-epitaxial region and in direct contact with the lower sinker regions. In this way no PN junctions are present inside the polycrystalline portion of the pseudo-epitaxial region and the structure has a high breakdown voltage.

Abstract: A programming method of a multilevel memory cell is able to store a plurality of bits in a plurality of levels. The method includes writing a logic value in the multilevel memory cell by setting one of the programming levels thereof, these levels being included in the plurality of levels, with respect to a reference level according to the symbol to be written and to a previous programming level. The writing step is repeated until a highest possible value for the levels is reached. A multilevel memory device includes a plurality of multilevel memory cells organized into sectors, split into a plurality of data units whereon a programming operation is performed in parallel.

Abstract: A sense amplifier structure for multi-level non-volatile memories reads the contents of the memory cells. In particular, a current drawn by a memory cell to be read is compared to a current drawn by a reference cell through a sense amplifier that has one input terminal connected to a circuit node to which said currents are led. Advantageously, the currents are compared at both inputs of the sense amplifier by connecting a second input of said amplifier to a circuit node to which said currents are led, with opposite signs. The method enhances the read precision of the sense amplifier for a given data acquisition time by doubling the differential input voltage.

Abstract: The present invention refers to a charge pump system supplied by a direct voltage signal and supplying on the output terminal a voltage signal with a higher value of said direct voltage signal.

Abstract: The integrated electronic device comprises a protection structure of metal, extending vertically and laterally to and along a predominant part of the periphery of an electronic component integrated underneath the pad region. The protection structure comprises a substantially annular region formed from a second metal layer and absorbing the stresses exerted on the pad during wire bonding. The annular region may be floating or form part of the path connecting the pad to the electronic component.

Abstract: The voltage applied to the gate terminals of the charging transistors and charge-transfer transistors of two parallel pumping branches forming a charge pump is a boosted voltage generated internally and supplied in a crosswise manner. In particular, for driving the charge pump, first and second driving signals are generated respectively for the first and for the second pumping branch via a first and respectively a second driving circuit; the first and second driving signals are also supplied respectively to a first and to a second auxiliary charge pump to obtain respectively first and second voltage-boosted signals; and the first and second boosted voltages are respectively supplied to the second and to the first driving circuit.

Abstract: The present invention refers to a circuit for current injection control comprising a first transistor having an input terminal, an output terminal and a control terminal, having the characteristic of comprising a second transistor having an input terminal connected to said output terminal of said first transistor, an output terminal and a control terminal and also comprising coupling means placed between said input terminal and said control terminal of said second transistor, said coupling means being active when said first and second transistor are in cut-off zone.

Abstract: A method for calibrating a frequency of a sigma-delta modulator having a go path that includes, in series, a resonator circuit and of an analog to digital conversion block, and a feedback path including a digital to analog conversion block, including the steps: a) applying an input pulse to the resonator circuit; b) measuring the oscillating frequency of the output signal from the resonator circuit in response to the pulse, while the feedback path of the sigma-delta modulator is opened; c) comparing the oscillating frequency of the resonator circuit with a selected frequency; d) modifying the oscillating frequency proportionately as a function of the comparison step. The resonator circuit includes an integrator filter with a variable gain amplifier in its feedback path, the variable gain configured to be modified as a function of the comparison, performed while the modulator feedback path is opened.

Abstract: A receiver for receiving digital signals exposed to intersymbol interference as well as multiple access interference the method including linearly detecting said signals by combating said intersymbol interference by equalizing said received digital signals as well as mitigating said multiple access interference by detecting said digital signals by means of sliding window detection.

Abstract: A package for a semiconductor device, comprising a leadframe on which at least one semiconductor chip is arranged, the semiconductor chip being connected to the leadframe by conducting leads and at least one ground lead; the ground lead is connected between the top of the semiconductor chip and a recessed region of the leadframe.

Abstract: For manufacturing an SOI substrate, the following steps are carried out: providing a wafer of semiconductor material; forming, inside the wafer, a plurality of passages forming a labyrinthine cavity and laterally delimiting a plurality of pillars of semiconductor material; and oxidizing the pillars of semiconductor material to form a buried insulating layer. For forming the labyrinthine cavity, a trench is first formed in a substrate; an epitaxial layer is grown, which closes the trench at the top; the wafer is annealed so as to deform the pillars and cause them to assume a minimum-energy handlebar-like shape, and a peripheral portion of the wafer is removed to reach the labyrinthine cavity, and side inlet openings are formed in the labyrinthine cavity. Oxidation is performed by feeding an oxidizing fluid through the side inlet openings.

Abstract: A quantum gate performs the superposition operation of a Grover's or of a Deutsch-Jozsa's quantum algorithm in a very fast manner. This is done by performing all multiplications by using logic gates that immediately outputs the result. The superposition operation includes performing the Hadamard rotation over an input set of vectors for producing a set of rotated vectors, and calculating the tensor product of all the rotated vectors for outputting a linear superposition set of vectors. The tensor product of all the rotated vectors is carried out by the logic gates.

Abstract: A selective silicidation process for electronic devices that are integrated on a semiconductor substrate is presented. The devices have a number of active elements formed with gate region that has at least one polysilicon layer. The process begins with depositing a dielectric layer over the entire surface of the semiconductor. Then portions of the dielectric layer are removed to expose the polysilicon layer in the gate regions. Next, a layer of a transition metal is deposited and subjected to a thermal treatment for selectively reacting it with the polysilicon layers and producing a silicide layer over the gate regions.

Abstract: A pulse programming method for a non-volatile memory device includes: addressing memory cells to be programmed within the device by selecting corresponding hierarchic decoder transistors; biasing the gate terminals of the memory cells; and programming the memory cells by applying a voltage pulse, regulated by a bias circuit, to the drain terminals of the memory cells. Advantageously, the programming method further comprises a step of precharging an internal node of the bias circuit before starting the programming step, the internal node being connected to a parasitic capacitance of the memory device.

Abstract: A process for the manufacturing of electronic devices, including memory cells, involving forming, on a substrate of semiconductor material, multilayer stacks including a floating gate region, an intermediate dielectric region, and a control gate region; forming a protective layer extending on top of the substrate and between the multilayer stacks and having a height at least equal to the multilayer stacks. The step of forming multilayer stacks includes the step of defining the control gate region on all sides so that each control gate region is completely separate from adjacent control gate regions. The protective layer isolates the multilayer stacks from each other at the sides. Word lines of metal extend above the protective layer and are in electrical contact with the gate regions.

Abstract: A processing architecture enables execution of one first set of instructions and one second set of instructions compiled for being executed by two different CPUs, the first set of instructions not being executable by the second CPU, and the second set of instructions not being executable by the first CPU. The architecture comprises a single CPU configured for executing both the instructions of the first set and the instructions of the second set. The single CPU in question being selectively switchable between a first operating mode, in which the single CPU executes the first set instructions, and a second operating mode, in which the single CPU executes the second set of instructions. The single processor is configured for recognizing a switching instruction between the first operating mode and the second operating mode and for switching between the first operating mode and the second operating mode according to the switching instruction.

Abstract: A switched capacitor digital to analog converter includes first and second converter segments having respective first and second arrays of binary weighted capacitors. Each capacitor of the first segment has a first electrode connected to a first common node and a second electrode connected through respective switches to one of first and second reference voltage terminals. Each capacitor of the second segment has a first electrode connected to a second common node and a second electrode connected through respective switches to one of the first and second reference voltage terminals. The converter includes a coupling capacitor connected between the first and second common nodes and capacitance means connected between the first common node and a reference voltage terminal.

Abstract: It is shown a low noise amplifier comprising a first circuit block suitable for converting a first amplifier input voltage signal into current, a second circuit block adapted to divide the current coming from said first block, said second block being controlled by a second voltage signal, said first and second blocks conferring a variable voltage gain to the amplifier. The amplifier comprises at least one first and at least one second resistors and a feedback network, said at least one first resistor connected with one first output terminal of said second block and with a supply voltage, and said at least one second resistor being connected between said at least one first and at least one second output terminals of said second block, and said feedback network being coupled with said at least one first terminal and with said first circuit block, and said at least one second terminal being coupled with at least one output terminal of said low noise amplifier.

Abstract: A method for manufacturing a thick oxide layer on a semiconductive substrate is presented. The method comprises the formation of at least one layer of dielectric material on said substrate, followed by formation of a plurality of trench regions of a predetermined width in the substrate. A plurality of corresponding walls of semiconductive material of a second predetermined width are delimited. Finally, the semiconductor is submitted to a thermal treatment to oxidize said walls.

Abstract: A method for generating a fault signal in a system voltage regulator by a phase signal includes detecting the system voltage and phase signal; comparing the system voltage and phase signal with respective fault levels; and generating a fault signal upon either the system voltage or the phase signal falling below the respective fault level of the fault levels. The fault signal generating method also inhibits generating a fault signal using a drive signal of the system voltage regulator. A diagnostic circuit for a system voltage regulator is also disclosed.