Abstract: A lateral DMOS transistor having a drain region which comprises a high-concentration portion with which the drain electrode is in contact and a low-concentration portion which is delimited by the channel region. In addition to the conventional source, drain, body and gate electrodes, the transistor has an additional electrode in contact with a point of the low-concentration portion of the drain region which is close to the channel. The additional electrode permits a direct measurement of the electric field in the gate dielectric and thus provides information which can be used both for characterizing the transistor and selecting its dimensions and for activating devices for protecting the transistor and/or other components of an integrated circuit containing the transistor.

Abstract: The manufacturing method comprises, in sequence, the steps of: depositing an upper layer of polycrystalline silicon; defining the upper layer, obtaining LV gate regions of low voltage transistors and undefined portions; forming LV source and drain regions laterally to the LV gate regions; forming a layer of silicide on the LV source and drain regions, on the LV gate regions, and on the undefined portions; defining stack gate regions and HV gate regions of high-voltage transistors; and forming HV source and drain regions and cell regions.

Abstract: A process fabricates a vertical structure high carrier mobility transistor on a substrate of crystalline silicon doped with impurities of the N type, the transistor having a collector region located at a lower portion of the substrate.

Abstract: The buffer has an output stage formed by two complementary MOS transistors connected so as to operate in phase opposition between the supply terminals and two driver stages having the input in common. Each driver stage has a first branch comprising a current-generator connected between the gate electrode of the transistor to be driven and a supply terminal and an electronic switch controlled by the input and connected between the same gate electrode and the other supply terminal, and a second branch which comprises, connected in series, a transistor connected as a diode and an electronic switch controlled by the output, and is arranged between the gate electrode of the transistor to be driven and a respective supply terminal. The buffer can control a load with a constant switching current, is simple in structure, and occupies a small area.

Abstract: A method of synchronizing the start of sequential read cycles when reading data in a memory in a synchronous mode with sequential access uses the increment pulses as synchronization signals for the address counters of the memory cell array. Following each increment pulse, a dummy ATD pulse is generated. The dummy ATD pulse is undistinguishable from an ATD pulse generated upon detection of a switching of external address lines.

Abstract: A current amplifier includes an input branch having a first input; an output branch coupled to said input branch; a bias branch suitable for biasing said input branch. The input branch comprises at least one switch commanded by a first bias voltage supplied by said bias branch so as to substantially block the current flowing in said input branch and consequently substantially block the current flowing in said output branch when the current applied to said first input is null.

Abstract: A hard disk read/write unit is formed in a monolithic body of semiconductor material, including a suspension structure, a coupling or flexure element integral with the suspension structure, and a microactuator, integral with the coupling. The monolithic body has a first portion accommodating integrated electronic components, and a second portion, accommodating the coupling and the microactuator. The coupling is formed from a central region, accommodating the microactuator; an annular region, separated from the central region by a first trench, and from the suspension by a second trench; a first pair of suspension arms, extending between the central region and the annular region, along a first axis; and a second pair of suspension arms, extending between the annular region and the suspension structure, along a second axis perpendicular to the first axis.

Abstract: A method for detecting the position of a rotor of a DC motor with N phases having a plurality of windings, comprising the steps of connecting two of the windings between first and second prefixed voltages through to a first current path for a prefixed time, allowing the current stored in the two windings to discharge through a second current path; comparing the voltage across one of the two windings with a reference voltage and providing a control signal when the voltage is smaller in absolute value than the reference voltage, performing the above steps for each of the winding pairs of the motor; detecting the position of the rotor on the basis of the control signals obtained.

Abstract: A method of improving the signal/noise ratio of a sigma-delta modulator during the re-establishment of its stability that includes: defining a bit sequence corresponding to a state of instability of the modulator, monitoring the flow of bits output by the modulator to check whether it contains the instability bit sequence, and resetting the modulator to zero if the instability bit sequence is detected at the output. To ensure a high signal/noise ratio of the modulator even during the detection and re-establishment of stability, the method also includes: delaying the flow of bits output by the modulator at least for the time required to detect the instability bit sequence and modifying the output bit sequence during the delay period by replacing it with a predetermined bit sequence.

Abstract: A switched capacitor digital-to-analog converter includes a first voltage generator for providing first and second reference voltages, a second voltage generator for providing third and fourth reference voltages selected to match predetermined design values of the first and second reference voltages, and an array of binary weighted capacitors. Each capacitor has a first electrode connected to a common circuit node, which is connected to a converter output terminal and a second electrode selectively connected, through an associated first switching circuit, to either one of the first and second reference voltages or, through an associated second switching circuit, to either one of the third and fourth reference voltages.

Abstract: A digital device for testing and calibrating the oscillation frequency of an integrated oscillator circuit, the testing and calibrating device has as input at least first and second control parameters corresponding to limiting values of a predetermined range of values of the oscillation frequency sought for the integrated oscillator circuit, and it includes a comparison circuit for comparing a signal of known duration and a signal from the integrated oscillator circuit; a circuit connected to the comparison circuit, for generating calibration values for the signal from the integrated oscillator circuit; and a circuit for forcing storage of final calibration values of the signal from the integrated oscillator circuit into a storage and control section of the integrated oscillator circuit.

Abstract: An exponentially variable gain mixer circuit includes an oscillating circuit generating an alternating differential signal. A correction circuit is connected to the oscillating circuit and includes a first amplifier and a differential amplifier. The first amplifier receives an external gain variation command and generates a differential output signal that includes a control voltage and a bias voltage. The differential amplifier receives the alternating differential signal and generates a differential modulation signal. A variable gain mixer receives an input differential signal and generates an amplified differential signal as a function of the differential modulation signal and the control voltage.

Abstract: Non-volatile, electrically alterable semiconductor memory, including at least one two-dimensional array of memory cells with a plurality of rows and a plurality of columns, column selection circuitry for selecting columns among the plurality of columns, and a write circuit for simultaneously writing a first number of memory cells. A plurality of doped semiconductor regions is provided, extending transversally to the rows and subdividing a set of memory cells of each row in a corresponding plurality of subsets of memory cells, each subset of memory cells including memory cells of the row formed in a respective doped semiconductor region distinct from the remaining doped semiconductor regions and defining an elementary memory block that can be individually erased.

Abstract: A method for controlling the level of a signal produced by a transceiver of digital data coupled to a power distribution line during a transmission phase is provided. The level of the signal output by the transceiver is regulated by comparing the current level of the output signal with a predetermined minimum threshold and a predetermined maximum threshold, reducing the current level when the maximum threshold is exceeded by reducing the gain, and switching to a voltage mode control of the output signal when the current level of the output signal becomes lower than the minimum threshold.

Abstract: The invention relates to a method of adjusting the erase/program voltage in semiconductor non-volatile memories. The memories are formed of at least one matrix of memory cells having a floating gate, a control gate, and drain and source terminals, and are organized by the byte in rows and columns, each byte comprising a group of cells having respective control gates connected in parallel with one another to a common control line through a selection element of the byte switch type, and each cell being connected to a respective control column through a selection element of the bit switch type. Advantageously, a double adjustment is provided for the program voltage of the memory cells, whereby the program voltage during the erasing phase can be higher in modulo than the program voltage during the writing phase.

Abstract: A vertical capacitor structure fabricated in a semiconductor substrate region overlaid by a buried oxide layer and a buried doped layer, as well as by a semiconductor layer that includes a sinker doped region in contact with the buried doped layer, wherein an oxide trench structure is formed, this oxide trench structure being filled with suitably doped polysilicon to produce, in combination with the sinker region, the plates of the vertical capacitor structure, with the oxide trench structure forming the dielectric therebetween. A process for integrating a vertical capacitor structure starting from a structure blank that includes a semiconductor substrate, a buried oxide layer and a buried doped layer is also provided.

Abstract: A circuit for providing a minimum wake-up time, in which a monostable circuit generates the WAKE-UP signal for a time at least as long as a minimum time established by the monostable circuit. The circuit is structured to extend the WAKE-UP signal for a time necessary to equal the minimum time that is established by the monostable circuit and to disable the WAKE-UP signal at the end of the variation of the input signal of the device being controlled.

Abstract: A read only memory (ROM) device includes a semiconductor substrate having a first type of conductivity, and a plurality of memory cells on the semiconductor substrate. Each memory cell includes first and second regions of a second conductivity type opposite the first conductivity type. A first dielectric layer is on the plurality of memory cells, and a plurality of first contacts extend through the first dielectric layer for contacting the first regions. A second dielectric layer is on the first dielectric layer and the plurality of first contacts. A plurality of second contacts extend through the second dielectric layer and overlie the corresponding second regions.

Abstract: A switched mode power supply having a first circuit provided with a primary winding of a transformer to which a pulse voltage is applied, a second circuit having a secondary winding of the transformer, a reactor provided with a magnetic core and which has a terminal connected to a terminal of the secondary winding, at least one filter provided with input and output terminals and a first diode connected in parallel to the input terminals of the filter is shown. The other terminal of the reactor is connected to a terminal of the first diode. The power supply includes a second diode that has a first terminal connected to the other terminal of the first diode and a second terminal connected to the other terminal of the secondary winding and a control circuit coupled to an output terminal of the filter and to the other terminal of the secondary winding. The control circuit generates a current able to reset the magnetic core of the reactor.

Abstract: A vertical-current-flow resistive element includes a monolithic region having a first portion and a second portion arranged on top of one another and formed from a single material. The first portion has a first resistivity, and the second portion has a second resistivity, lower than the first resistivity. To this aim, a monolithic region with a uniform resistivity and a height greater than at least one of the other dimensions is first formed; then the resistivity of the first portion is increased by introducing, from the top, species that form a prevalently covalent bond with the conductive material of the monolithic region, so that the concentration of said species becomes higher in the first portion than in the second portion. Preferably, the conductive material is a binary or ternary alloy, chosen from among TiAl, TiSi, TiSi2, Ta, WSi, and the increase in resistivity is obtained by nitridation.