Abstract: An electrical connection structure having connection elements which electrically connect a movable part to a fixed part of a microelectromechanical device, for example a microactuator. The movable part and fixed part are separated by trenches and are mechanically connected by spring elements, which determine, together with the connection elements, the torsional rigidity of the microelectromechanical device. Each connection element is formed by multiple sub-arms connected in parallel and having a common movable anchorage region anchored to the movable part, and a common fixed anchorage region anchored to the fixed part, whereby the mechanical resistance of the connection elements is negligible. The sub-arms have a width equal to a sub-multiple of the width necessary in case of a single connection element for the latter to have a preset electrical resistance, which is determined in the design.

Abstract: High-Q, variable capacitance capacitor is formed by including a pocket of semiconductor material; a field insulating layer, covering the pocket; an opening in the field insulating layer, delimiting a first active area; an access region formed in the active area and extending at a distance from a first edge of the active area and adjacent to a second edge of the active area. A portion of the pocket is positioned between the access region and the first edge and forms a first plate; an insulating region extends above the portion of said body, and a polysilicon region extends above the insulating region and forms a second plate. A portion of the polysilicon region extends above the field insulating layer, parallel to the access region; a plurality of contacts are formed at a mutual distance along the portion of the polysilicon region extending above the field insulating layer.

Abstract: MOS-gated power device including a plurality of elementary functional units, each elementary functional unit including a body region of a first conductivity type formed in a semiconductor material layer of a second conductivity type. A plurality of doped regions of a first conductivity type is formed in the semiconductor material layer, each one of the doped regions being disposed under a respective body region and being separated from other doped regions by portions of the semiconductor material layer.

Abstract: A multipurpose memory device suitable for a broader range of applications, whether requiring the reading of data in an asynchronous mode with random access (as in a standard memory) or in a synchronous sequential mode with sequential or burst type access, is capable of recognizing the mode of access and the mode of reading that is currently required by the microprocessor. The memory device self-conditions its internal circuitry as a function of such a recognition in order to read data in the requested mode without requiring the use of additional external control signals and/or implying a penalization in terms of access time and reading time compared to those which, for the same fabrication technology and state of the art design, may be attained with memory devices specifically designed for either one or the other mode of operation.

Abstract: A non-volatile semiconductor memory device that includes an address buffer block, a matrix of memory cells, and an output buffer block. The address buffer block receives input signals external to the memory device, that in a first operating mode are controlled by devices outside to the memory device, and transmit signals to the matrix of memory cells, which are adapted to decode the received signals and to transmit in turn output decoded signals through the output buffer block. A command block is provided that is activatable through an external control signal and once activated, it puts the memory device in a second operating mode in which the command block receives at least a part of the signals in output of said matrix of memory cells and, after having processed them, transmits internal address signals to the address buffer block. This provides a feedback inside the memory device capable of making the same able to autonomously execute a succession of instructions stored in the matrix of memory cells.

Abstract: An injection control method for controlling a “common rail” fuel injection system in a diesel engine is described. The method includes the following steps: an initializing step for acquiring engine control parameters; and a main adjustment cycle for adjusting operational variables of the engine. The injection control method also includes an interrupting step for adjusting an injection procedure proper of the injection system by variation of all the characteristic parameters of the injection procedure. Also described is an injection control system for a diesel engine based on the above method.

Abstract: A process for fabricating a dual charge storage location, electrically programmable memory cell, comprising: forming a first dielectric layer over a semiconductor material layer of a first conductivity type; forming a charge trapping material layer over the first dielectric layer; selectively removing the charge trapping material layer from over a central channel region of the semiconductor material layer, thereby leaving two charge trapping material layer portions at sides of the central channel region; masking the central channel region and selectively implanting dopants of a second conductivity type into the semiconductor material layer to form memory cell source/drain regions at sides of the two charge trapping material layer portions; forming a second dielectric layer over the charge trapping material layer; and forming a polysilicon gate over the second dielectric layer, the polysilicon gate being superimposed over the central channel region and the two charge trapping material layer portions.

Abstract: A voltage/current controller device, particularly for interleaving switching regulators, comprises: a DC/DC converter having a plurality of modules, with each module including a drive transistor pair connected in series between first and second supply voltage references, a current sensor connected to one transistor in the pair, and a current read circuit connected to the sensor. Advantageously, the read circuit comprises a transconductance amplifier connected across the current sensor to sense a voltage signal related to a load current being applied to each module, the transconductance amplifier reading the voltage signal with the transistor in the conducting state.

Abstract: The invention relates to a circuit generating a voltage signal which is independent of temperature and has low sensitivity to variations in process parameters, comprising at least an output MOS transistor through which an output current flows, it being connected to a first voltage reference and having a gate terminal connected to a bias network, in turn connected between a second voltage reference and the first voltage reference. The circuit of this invention includes a bias network comprising at least first and second MOS transistors connected in a diode configuration, connected in series between said first and second voltage references, and connected to the second voltage reference through a current generator element having a thermal gradient that approximates the thermal gradient of a MOS transistor.

Abstract: A capillary for electrical bonding between a semiconductor chip and corresponding pins of a semiconductor device in which the chip is accommodated includes a body whose terminal portion is substantially frustum-shaped. The body has a diametrical through hole which allows the passage of a copper wire for electrical bonding between the chip and the semiconductor device. The portion of the body that is adjacent a lower end of the through hole is flared, with a flaring diameter and a flaring angle which allows formation of a substantially flat annular peripheral region on a copper ball when the copper ball is placed at a lower end of the copper wire. The copper ball is deformed by the action of the capillary. The formation of the substantially flat annular peripheral region is independent of the position of the copper wire within the through hole of the body of the capillary.

Abstract: Process for forming salicide on active areas of MOS transistors, each MOS transistor comprising a gate and respective source and drain regions, the source and drain regions each comprising a first lightly doped sub-region adjacent the gate and a second highly doped sub-region spaced apart from the gate. The salicide is formed selectively at least over the second highly doped sub-regions of the source and drain regions of the MOS transistors, and not over the first lightly doped sub-region.

Abstract: An inductive structure integrated in a semiconductor substrate, comprising at least a conductive element insulated from the substrate, comprising an insulating structure, which is formed inside said semiconductor substrate and built close to said conductor element, so that the resistance of said substrate is increased and the parasitic currents induced by the conductor element in the substrate are decreased. The insulating structure including a plurality of insulating elements each surrounding a respective one of a plurality of semiconductor islands of the substrate.

Abstract: An integrated circuit contains a processor (DSP) for the processing of data, at least two modules (M1, M2, M3) for the processing of data packets selected by the processor according to differing operation regulations, and a router (ROUTER) which is connected to all modules (M1, M2, M3) and to the processor (DSP) for the purpose of controlling the data traffic between the processor (DSP) and the modules (M1, M2, M3). The router is suited to receive from the processor (DSP) data packets and associated instructions, to execute special operations for individual data packets which can be executed by the modules (M1, M2, M3) in specified sequence, to coordinate autonomously the control of the sequences, to transfer the data packets to the appropriate modules (M1, M2, M3), and to transfer the data packets after they have been processed according to the specified instructions to the processor (DSP).

Abstract: A semiconductor memory architecture having two memory banks each containing respective memory locations, and for each memory bank, respective circuits for selecting the locations of the bank and respective circuits for reading the data contained in the selected locations of the bank, a structure for the transfer of the data read by the reading circuits associated with the memory banks to data output terminals of the memory, there being a single data-transfer structure assigned selectively to one memory bank at a time and which includes storage for storing the most recent datum read by the reading circuits, and output driver circuits activated selectively in order to transfer the contents of the registers to the data output terminals of the memory, an addressing structure having, for each memory bank, and a respective circuit for the sequential scanning of the memory locations of the bank, operatively connected to the respective circuits for selecting the locations of the memory bank.

Abstract: A process for selectively sealing ferroelectric capacitive elements in non-volatile memory cells being integrated in a semiconductor substrate and comprising at least one MOS transistor, which process comprises at least the following steps: forming said at least one MOS transistor on the semiconductor substrate, and depositing an insulating layer over the whole surface of the semiconductor; and further comprises the steps of: depositing a first metal layer to form, using a photolithographic technique, a lower electrode of at least one ferroelectric capacitive element; depositing a layer of a dielectric material onto said first layer; depositing a second metal layer to form, using a photolithographic technique, an upper electrode of at least one ferroelectric capacitive element; depositing a layer of a sealing material onto said second metal layer; defining the dielectric material layer and sealing layer by a single photolithographic defining step, so as to pattern said dielectric layer and concurrently seal s

Abstract: A FLASH memory is organized in a plurality of physical sectors which may be split into a plurality of singularly addressable logic sectors. Each logic sector may include a memory space of a predetermined size and a chain pointer assuming a neutral value or a value pointing to a second logic sector associated with a respective chain pointer at the neutral value. Each logic sector may also include a status indicator assuming at least one of a first value if the logic sector is empty, a second value if the data therein belongs to the logic sector, a third value if the data does not belong to the logic sector, and a fourth value if the data has been erased. Further, each logic sector may include a remap pointer assuming the neutral value or a value pointing directly or indirectly to the chain pointer of a third logic sector.

Abstract: A method of producing a protective inhibitor layer of moisture-generated corrosion for aluminum (Al) alloy metallization layers, particularly in semiconductor electronic devices, includes chemically treating the metallization layer in at least two steps using a mixture of concentrated nitric acid and trace phosphoric acid to produce a thin protective phosphate layer. Alternatively, the method may include dipping the electronic device at least once in a mixture of a polar organic solvent and phosphoric acid (H3PO4) or phosphate derivatives thereof in a low percentage amount (e.g., with a phosphate reactant such as orthophosphoric acid or even R—HxPOy, where R is an alkaline type of ion group or an alkyl radical). The thin film may be formed on top of a thin layer of native aluminum oxide hydrate Al2O3.xH2O.

Abstract: A charge pump circuit, connected between a first voltage reference and an output terminal, comprises at least two stages comprising an elementary charge pump circuit connected between said first voltage reference and said output terminal, and adjustment circuitry connected between said output terminal and respective control terminals of said at least two stages. This circuitry is arranged to select for actuation an appropriate combination of these elementary stages according to the current absorbed from a load connected to the output terminal.

Abstract: Presented is a method for obtaining a multi-level ROM in a dual gate EEPROM process flow. The method begins with, on a semiconductor substrate, defining active areas respectively for transistors of ROM cells, transistors of electrically erasable non-volatile memory cells, and additional transistors of the storage circuitry. Then, integrated capacitors are integrated in the storage circuit. According to this method, during the implanting step for forming integrated capacitors, at least an active area of the ROM cell is similarly implanted.

Abstract: An electronic device including a microprocessor, a circuit generating a clock signal, and memories of both the volatile type and the non-volatile type, incorporates a circuit for generation of a reset signal capable of detecting a stop in the oscillation of said clock signal and generating a logic signal coupled with the reset input of the microprocessor. The circuit monitors the clock signal applied to the device and, if an irregularity is detected, generate a reset signal holding the microprocessor in a safe state. The reset signal is held until the circuit generating the clock signal resumes normal operation.