Abstract: The memory cell is of the type with a single level of polysilicon, and comprises a sensing transistor and a select transistor. The sensing transistor comprises a control gate region with a second type of conductivity, formed in a first active region of a substrate of semiconductor material, and a floating gate region which extends transversely relative to the first active region. The control gate region of the sensing transistor is surrounded by a first well with the first type of conductivity, and in turn is surrounded, below and laterally, by a second well with the second type of conductivity, thus forming a triple-well structure. A second triple-well structure can be formed in a second active region adjacent to the first active region, and can accommodate conduction regions of the sensing transistor and of the select transistor.

Abstract: A high side circuit includes at least one power device having a first non-drivable terminal connected to a supply voltage, at least one load connected between a second non-drivable terminal of the power device and ground, and driving circuitry. The driving circuitry includes transistors which are connected to each other and to a higher voltage than the supply voltage in order to control the turning on and the turning off of the power device and to reduce or minimize the potential difference between the second non-drivable terminal and a drivable terminal of the power device during the turning off state to avoid the re-turning on of the same power device.

Abstract: A sensing device having a microelectromechanical structure made of semiconductor material, and a control loop for controlling the microelectromechanical structure, the microelectromechanical structure including a stator element and a rotor element electrostatically coupled together, and the control loop including a position interface supplying a position signal indicative of the position of the rotor element, and a one-bit quantizer receiving the position signal and supplying a corresponding bit sequence. The sensing device further includes a calibration device for calibrating the microelectromechanical structure, including a microactuator made of semiconductor material and coupled to the rotor element, and a driving circuit for driving the microactuator, and receiving the bit sequence and supplying to the microactuator a driving signal correlated to a mean value of the bit sequence in a given time window.

Abstract: A driver circuit drives a power element connected to an inductive load. The driver circuit includes an input terminal coupled to a control terminal of the power element through a trigger block, and a voltage regulator block having a circuit node coupled to a first supply voltage reference, as well as to a second supply voltage reference through a capacitor. A voltage comparator stage includes an operational amplifier having an inverting input connected to the circuit node and a non-inverting input is connected directly to a terminal of the power element, such as to the emitter terminal thereof. The operational amplifier also includes an output connected to the control terminal of the power element.

Abstract: The programming method includes the following steps: sequentially receiving a plurality of data words; temporarily storing each data word after its reception; and simultaneously writing in parallel the plurality of stored data words in a memory array. After reception and temporary storage of each data word, the memory increments an address counter and sends a “ready” signal. Upon reception of each new data word, the memory verifies whether the address associated thereto is in the same sector as the initial data word and whether n data words have already been stored. If the sector is different, blind-programming step is terminated and the verifying is carried out; if the sector is the same but n data words have already been stored temporarily, the memory writes the temporarily stored words in the memory array, updates the address counter, and then sends the “ready” signal.

Abstract: Described is a method to form isolation structures on a semiconductor substrate. This method begins with forming one or more trenches in the semiconductor substrate and depositing a first portion of a dielectric layer at a first rate by a High Density Plasma—Chemical Vapor Deposition into the trenches and onto the semiconductor substrate. This first deposition at least partially fills the trenches and may completely fill the trenches. Next, a second portion of the dielectric layer is deposited at a second rate by the High Density Plasma—Chemical Vapor Deposition over the semiconductor substrate to partially planarize the dielectric layer. This second deposition is preferably performed with a different flow rate of reaction gasses than the first deposition. Finally, a portion of the dielectric layer that was deposited at the second rate is removed by a CMP process, for example.

Abstract: A process that provides for the manufacture of LV transistors with salicidated junctions on first areas of a substrate, HV transistors on second areas, and memory cells on third areas. The process includes forming LV oxide regions and LV gate regions on the first areas, HV oxide regions on the second areas, selection oxide regions, tunnel oxide regions, and matrix oxide regions on the third areas; forming floating gate regions and insulating regions on the tunnel oxide regions and the matrix oxide regions; forming first LV source and drain regions laterally to the LV gate regions; forming silicide regions on the first source and drain regions and on the LV gate regions; forming semiconductor material regions completely covering the second and third areas; and at the same time forming HV gate regions on the HV oxide regions, forming selection gate regions on the selection oxide regions, and forming control gate regions on the insulating regions through shaping of the semiconductor material regions.

Abstract: A read timing circuit regulates the step of reading from a multi-level non-volatile memory, which circuit is of a type adapted to generate and issue an equalization signal to a sense amplifier placed downstream of a dummy path including at least one dummy wordline, the latter being applied a supply voltage and associated with a dummy decoding circuit portion which receives an ATD signal. The circuit comprises a differential cell comparator having a first input connected downstream of the dummy path and a second input to receive a reference signal, thereby generating an electric signal on an output upon the dummy wordline attaining a potential which is a predetermined percent of the supply voltage.

Abstract: Method for fabricating integrated circuits comprising non-volatile memory cell matrices and peripheral circuits, said method comprising the steps of preparing a silicon substrate, carrying out a shallow trench isolation process on the silicon substrate to form active areas of exposed silicon isolated from one another by trenches filled with field oxide, growing a thin oxide layer on the active areas, masking the substrate areas intended for the memory cell matrices and etching the thin oxide layer and the field oxide by a chemical etch for a time longer than the time needed for removing the thin oxide layer entirely from the substrate areas intended for the peripheral circuits.

Abstract: A pointer circuit for pointing to elements in at least one collection of elements comprises a base pointer adapted to provide a first binary-coded value defining a first address of an element in the collection. The pointer circuit also comprises a binary shift circuit receiving the first binary-coded value provided by the base pointer and a second binary-coded value defining a shift value. The binary shift circuit combines the first and second binary-coded values to provide a third binary-coded value defining a second address of an element in the collection differing from the first address by the shift value. A shift value generator fed by the first binary-coded value generates the second binary-coded value depending on the first binary-coded value, in such a way that a generated shift value takes into account shift values corresponding to first binary-coded values preceding a current first binary-coded value in a prescribed first binary-coded value progression order.

Abstract: An electronic device having first and second external pins; first and second pads connected to the first external pin by respective bonding wires; and third and fourth pads connected to the second external pin respective bonding wires, and to a first common line by respective resistors. By means of a circuit configuration of this type, the intactness of the bonding wires can easily be checked by carrying out a simple resistance measurement between the first and the second external pin.

Abstract: A process for fabricating non-volatile memory cells on a semiconductor substrate includes forming a stack structure comprised of a first polysilicon layer isolated from the substrate by an oxide layer. The first polysilicon layer, oxide layer, and semiconductor substrate are cascade etched to define a first portion of a floating gate region of the cell and at least one trench bordering an active area of the memory cell. The at least one trench is filled with an isolation layer. The process further includes depositing a second polysilicon layer onto the whole exposed surface of the semiconductor, and etching the second polysilicon layer to expose the floating gate region formed in the first polysilicon layer, thereby forming extensions adjacent the above portion of the first polysilicon layer.

Abstract: The device is for driving and controlling a rotation motor and a voice coil motor for a hard disk drive system that includes a disk and an arm carrying a read/write head to be positioned with respect thereto. A duty-cycle control loop including a current sensing circuit is connected to the voice coil motor, and an arm position control loop including a speed detection circuit is also connected to the voice coil motor. The duty-cycle control loop and the arm position control loop are digitally implemented by a DSP as a function of digital data representing a first analog signal generated by the current sensing circuit representative of current conducting in a winding of the voice coil motor, and a second analog signal generated by the speed detection circuit representative of an instant speed of the voice coil motor.

Abstract: A memory device including a plurality of memory cells, a plurality of insulated first regions of a first type of conductivity formed in a chip of semiconductor material, at least one second region of a second type of conductivity formed in each first region, a junction between each second region and the corresponding first region defining a unidirectional conduction access element for selecting a corresponding memory cell connected to the second region when forward biased, and at least one contact for contacting each first region; a plurality of access elements are formed in each first region, the access elements being grouped into at least one sub-set consisting of a plurality of adjacent access elements without interposition of any contact, and the memory device further includes means for forward biasing the access elements of each sub-set simultaneously.

Abstract: An impedance control circuit controls the impedance of an integrated output driving stage. The integrated output driving stage includes at least one enabling/disabling transistor and at least one driving transistor. The impedance control circuit includes a variable impedance circuit having an impedance that varies with the temperature in correlation with the impedance of the output driving stage. A control circuit is connected to the variable impedance circuit for generating at least one enabling/disabling signal for the at least one enabling/disabling transistor based upon a control signal correlated to the impedance of the variable impedance circuit. The impedance control circuit also includes a current generating circuit for applying to the variable impedance circuit a current which remains substantially stable as the temperature varies.

Abstract: A resistive structure integrated on a semiconductive substrate is described. The resistive structure has a first type of conductivity formed into a serpentine region of conductivity which is opposite to that of the semiconductive substrate. In at least two parallel portions of the serpentine region, there is at least one trench filled with an insulating material.

Abstract: A circuit for sensing a ferroelectric non-volatile information storage unit comprises a pre-charge circuit for applying a prescribed pre-charge voltage to a storage capacitor of the information storage unit. The pre-charge voltage causes a variation in a polarization charge of the storage capacitor, depending on an initial polarization state of the storage capacitor. A charge integration circuit integrates an electric charge proportional to the variation in polarization charge experienced by the storage capacitor. The charge integration circuit thus provides an output voltage depending on the polarization state of the storage capacitor.

Abstract: A method of sensing a ferroelectric non-volatile information storage unit comprising two ferroelectric storage capacitors in mutually opposite polarization states, and a sensing circuit for actuating the method.

Abstract: An architecture of a nonvolatile memory device, though not requiring dedicated pins and by introducing circuit modifications that require a negligible additional silicon area in the serial interface, allows a selection between at least two different serial communication protocols, thus multiplying the occasions of employment of the same device. The selection of one or of the another serial communication protocol is carried out by setting, during the testing on wafer (EWS) of the devices being fabricated, a certain UPROM cell of the array of UPROM cells that is normally present in a standard nonvolatile memory device for setting during the fabrication the characteristics of ATD, redundancy and other functions of the memory device. Alternatively, the customer can make the selection by placing an appropriate signal level on a specified pin of the memory device.

Abstract: A reading circuit for semiconductor non-volatile memories connected to at least one selected cell and at least one reference cell, the circuit including current/voltage conversion circuits receiving a first current flowing through the selected cell and a second current flowing through the reference cell and providing respectively on a first circuit node a first selected cell voltage and on a second node a second reference cell voltage, at least one differential amplifier connected at the input of the first and the second nodes and having an output terminal to provide a logic signal correlated to the selected cell information, a first voltage-controlled discharge switch circuit connected to the first node and to a voltage reference, a second switch circuit connected to the second node and the voltage reference, and first and second voltage comparator circuits receiving the first selected cell voltage and the second reference cell voltage.