Abstract: A process including the steps of: carrying out a directional etching in a semiconductor material body to form trenches having a first width; carrying out an isotropic etching of the semiconductor material body under the trenches to form cavities having a width larger than the trenches; covering the walls of the cavities with dielectric material; depositing non-conducting material different from thermal oxide to fill the cavities at least partially, so as to form a single-crystal island separated from the rest of the semiconductor material body. The isotropic etching permits the formation of at least two adjacent cavities separated by a support region of semiconductor material, which is oxidized together with the walls of the cavities to provide a support to the island prior to filling with non-conducting material.

Abstract: Herein described is a driver circuit of a fluorescent lamp having a first and a second electrode and igniting when the voltage between the first and second Electrode exceeds a given threshold voltage. The driver circuit comprises an inductance coupled to a supply voltage and to a terminal of the first electrode a first condenser coupled to the other terminal of the first electrode and to a terminal of the second electrode, a control device comprising a first and a second system of switches capable of guaranteeing oscillations of a voltage signal on the inductance and on the first condenser up to the ignition of the lamp. The driver circuit comprises a device associated to the control device and capable of acting on the first system of switches so as to regulate the frequency of the oscillations from a frequency greater than the resonance frequency of the inductance and of the first condenser to the same resonance frequency so as to guarantee a preheating of the first and second electrodes.

Abstract: A switch-type regulator with a soft-start function having an output terminal supplying an output voltage, and including an error amplifier, having a first input receiving a constant reference voltage, a second input receiving a feedback voltage dependent on the output voltage, and supplying a compensation terminal with an error voltage correlated to the difference between the reference voltage and the feedback voltage. The error amplifier includes a differential amplifier. The regulator also includes a compensation network connected to the compensation terminal. A soft-start function is obtained exploiting the compensation network.

Abstract: High-Q, variable capacitance capacitor is formed by including a pocket of semiconductor material; a field insulating layer, covering the pocket; an opening in the field insulating layer, delimiting a first active area; an access region formed in the active area and extending at a distance from a first edge of the active area and adjacent to a second edge of the active area. A portion of the pocket is positioned between the access region and the first edge and forms a first plate; an insulating region extends above the portion of said body, and a polysilicon region extends above the insulating region and forms a second plate. A portion of the polysilicon region extends above the field insulating layer, parallel to the access region; a plurality of contacts are formed at a mutual distance along the portion of the polysilicon region extending above the field insulating layer.

Abstract: A process for encoding digital video signals organized in frames comprises the operations of dividing said frames into blocks starting from macroblocks subjected to motion-compensation and applying to said blocks a discrete cosine transform in such a way as to generate respective sets of coefficients. The said sets of coefficients are then assembled by being organized into sets of vectors by means of masking. Once the variance of the vectors has been detected, the vectors themselves are quantized on a number of available bits by means of a pyramid vector quantizer, associating to the vectors respective quantization pyramids having given sizes according to the variance detected and to the number of available bits. Finally, the vectors are encoded with respective codewords.

Abstract: A circuit structure for reading data contained in an electrically programmable/erasable integrated non-volatile memory device includes a matrix of memory cells and at least one reference cell for comparison with a memory cell during a reading phase. The reference cell is incorporated in a reference cells sub-matrix which is structurally independent of the matrix of memory cells. Also provided is a conduction path between the matrix and the sub-matrix, which path includes bit lines of the sub-matrix of reference cells extended continuously into the matrix of memory cells.

Abstract: A semiconductor memory device having at least one memory cell row, each memory cell having an information storing element and a related select transistor for selecting the storing element. The select transistor includes a gate oxide region over a silicon substrate, a lower polysilicon layer and an upper polysilicon layer superimposed to the gate oxide region and electrically insulated by an intermediate dielectric layer interposed therebetween. The gate oxide regions of the select transistors of the at least one row are separated by field oxide regions, and the lower and upper polysilicon layers and the intermediate dielectric layer extend along the row over the gate oxide regions of the select transistors and over the field oxide regions. Along the row there is at least one opening in the upper polysilicon layer, intermediate dielectric layer and lower polysilicon layer, inside of which a first contact element suitable to electrically connect the lower and upper polysilicon layers is inserted.

Abstract: A fully digital phase aligner includes a control loop acting upon a delay line comprising at least a cascade of delay cells, each cell being individually configurable to produce one of two selectable propagation delays as a function of the logic state of a respective digital control signal. This is done by way of a shift register including a number of latches equal to the number of the cells of the delay line. An output tap of each latch of the shift register controls a respective delay cell of the delay line. A digital state machine in the control loop prevents any undesired oscillations.

Abstract: A method for compressing encoding data of a sequence of pictures is based on a motion estimation among the successive images to remove the temporal redundancy from the data. The method recognizes a 3:2 pulldown conversion of a series of photograms of a filmed sequence in a sequence of TV frames. The TV frames have a number greater than the number of the photograms by duplicating certain pictures in a certain order. The redundancy due to such picture duplications is eliminated.

Abstract: A process for manufacturing a semiconductor memory device includes double polysilicon level non-volatile memory cells and shielded single polysilicon level non-volatile memory cells in the same semiconductor material chip. A first memory cell includes a MOS transistor having a first gate electrode and a second gate electrode superimposed and respectively formed by definition in a first and a second layer of conductive material. A second memory cell is shielded by a layer of shielding material for preventing the information stored in the second memory cell from being accessible from the outside. The second memory cell includes a MOS transistor with a floating gate electrode formed simultaneously with the first gate electrode of the first cell by definition of the first layer of conductive material. The layer of shielding material is formed by definition of the second layer of conductive material.

Abstract: A timing and control structure for a memory, including the timing and control structure includes a first circuit that can recognize, on the basis of control signals supplied to the memory from the exterior, whether a random-access reading is to be executed, the control signals including a first control signal indicative of the presence of an address supplied to the memory from the exterior, and a second control signal that, upon switching edges of a first type, supplies to the control and timing structure a time base for the execution of the random-access readings and, upon switching edges of a second type, supplies a time base for the execution of the sequential readings, a second circuit controlled by the first circuit and upon a random-access reading, generates a first synchronism signal in response to a transition of the first type in the second control signal, a third circuit sensitive to transitions of the second type in the second control signal and which can generate a second synchronism signal upon t

Abstract: The lateral DMOS transistor is integratable in a semiconductor power device comprising a P-type substrate and an N-type epitaxial layer. The lateral DMOS transistor comprises a source region and a drain region formed in the epitaxial layer and a body region housing the source region. Between the source region and the drain region is present an insulating region extending in depth from a top surface of the epitaxial layer as far as the substrate. The insulating region presents an interruption in a longitudinal direction defining a channeling region for a current ID flowing between the source region and the drain region of the lateral DMOS transistor.

Abstract: A control circuit providing a driving current to a voice coil motor to position a reading and writing head of a disk memory system is described. The circuit comprises a first and a second class AB amplifiers the outputs of which are connected to the terminals of a first resistor in series with the voice coil motor so that a current passes through the voice coil motor and through the first resistor. The circuit comprises a sense amplifier the input terminals of which are coupled with the terminals of said first resistor, a device at the input of which is present a signal which is a sum of an external signal and of an output signal of the sense amplifier. The first amplifier and the second amplifier being driven in inverted phase by an output signal produced by the device.

Abstract: A circuit for generating a constant pulse signal from an enabling ATD input signal may include a latch structure connected between first and second circuit nodes, with each node being coupled to a corresponding charge and discharge capacitance and being also connected to respective inputs of a logic gate. The circuit may also include a memory element coupled to the circuit nodes for filtering the enabling ATD signal and avoiding a partial discharge of one of the capacitances. An output of the logic gate is provided for generating the pulse signal independent of voltage and/or temperature variations affecting the enabling ATD signal.

Abstract: A power modulation control system using PWM pulses is provided. The system comprises an AC voltage generator, an electric load, and a control circuit incorporating at least one rectifier. The electric load is connected between the generator and the rectifier, and first and second monodirectional switches are connected in parallel with the load.

Abstract: A currency note includes an identification and/or authentication element including an integrated circuit. The integrated circuit can store, securely in electronic form and accessible from outside, such information as: the value, serial number, issuer, and date of issuance.

Abstract: An inertial sensor having a stator and a rotor made of semiconductor material and electrostatically coupled together, and a microactuator also made of semiconductor material, coupled to the rotor and controlled so as to move the rotor itself and thus compensate for the position offset thereof.

Abstract: An EEPROM memory cell integrated in a semiconductor substrate comprises a floating gate MOS transistor having a source region, a drain region, and a gate region projecting from the substrate and is isolated from the substrate by an oxide layer including a thinner tunnel portion and heavily doped regions formed under said tunnel portion and extending to beneath the drain region, and a selection transistor having a source region, a drain region and a gate region, wherein said source region is heavily doped and formed simultaneously with said heavily doped regions.

Abstract: Data are converted between an unencrypted and an encrypted format according to the Rijndael algorithm, including a plurality of rounds. Each round is comprised of fixed set of transformations applied to a two-dimensional array, designated state, of rows and columns of bit words. At least a part of said transformations are applied on a transposed version of the state, wherein rows and columns are transposed for the columns and rows, respectively.

Abstract: The electronic ignition device includes an ignition coil with a primary winding terminal and a secondary winding terminal generating a spark, a power element arranged between the primary winding terminal and ground, a protection circuit issuing a disable signal to the control terminal of the power element in preset conditions, and a voltage limiting circuit having inputs connected to the primary winding terminal and to the battery voltage, and an output connected to the control terminal of the power element. The voltage limiting circuit detects a potential difference between its own inputs and supplies to the control terminal an activation signal for the power element, in presence of the deactivation signal and when the potential difference exceeds the supply voltage by a preset value. Thereby, the voltage limiting circuit limits the voltage on the primary winding terminal to a preset value which depends upon the value of the battery voltage.