Abstract: The electronic ignition device includes an ignition coil with a primary winding terminal and a secondary winding terminal generating a spark, a power element arranged between the primary winding terminal and ground, a protection circuit issuing a disable signal to the control terminal of the power element in preset conditions, and a voltage limiting circuit having inputs connected to the primary winding terminal and to the battery voltage, and an output connected to the control terminal of the power element. The voltage limiting circuit detects a potential difference between its own inputs and supplies to the control terminal an activation signal for the power element, in presence of the deactivation signal and when the potential difference exceeds the supply voltage by a preset value. Thereby, the voltage limiting circuit limits the voltage on the primary winding terminal to a preset value which depends upon the value of the battery voltage.

Abstract: A buffer having a circuit for reducing the slope of an input signal and a negative feedback circuit that generates a regulating signal dependent on the variation of the output signal and that applies the regulating signal to the input of the buffer. A precise regulation of the slope, independent of variations in the production process and of environmental conditions, is achieved.

Abstract: The invention relates to a circuit for highly efficient driving of piezoelectric loads, comprising a linear driving circuit portion connected to the load through an inductive-resistive connection whereto a voltage waveform is applied. Advantageously, the circuit comprises further respective circuit portions, structurally independent, connected in turn to the inductive-resistive connection through respective inductors to supply a considerable fraction of the overall current required by the load in the transient and steady state respectively.

Abstract: A method compresses a digital image including a matrix of elements each one including a plurality of digital components of different type representing a pixel. The method includes the steps of providing an incomplete digital image wherein at least one component is missing in each element, obtaining the digital image from the incomplete digital image, splitting the digital image into a plurality of blocks and calculating, for each block, a group of DCT coefficients for the components of each type, and quantizing the DCT coefficients of each group using a corresponding quantization table scaled by a gain factor for achieving a target compression factor. The method further comprises the steps of determining an energy measure of the incomplete digital image and estimating the gain factor as a function of the energy measure, the function being determined experimentally according to the target compression factor.

Abstract: A multilevel nonvolatile memory includes a supply line (28) supplying a supply voltage (VDD), a voltage boosting circuit (26) supplying a boosted voltage (Vp), higher than the supply voltage (VDD), a boosted line (30) connected to the voltage boosting circuit (26) and a reading circuit (25) including at least one comparator (35). The comparator (35) includes a first and a second input (35a, 35b), a first and a second output (45a, 45b), at least one amplification stage (40) connected to the boosted line (30), and a boosted line latch stage (41) connected to the supply line (28).

Abstract: A start-up procedure for a multiphase brushless motor to be accelerated until reaching a certain speed includes determining the starting position of the rotor and performing an excitation phase including forcing a drive current in the phase windings of the motor for an established period of time. This is done according to a switching sequence for inducing a rotation in the desired direction. Furthermore, the method may include sensing the position reached by the rotor at the end of each excitation phase. The start-up procedure is eventually interrupted when the established speed has been reached or exceeded. Additionally, the duration of a next phase of excitation may be increased or reduced, and the switching sequence may be modified, based upon the number of consecutive times in which the current position is found to be the same or different from the previously detected position, respectively.

Abstract: An operational amplifier includes a first stage, and a second stage with an input connected to an output of the first stage and an output connected to a load. The second stage includes between its input and its output a first signal path for driving the load in a first direction, and a second signal path for driving the load in the opposite direction. The first and second signal paths have substantially equal gains for small signals, substantially equal output impedances for small and large signals, and substantially equal output-current capabilities.

Abstract: A driving circuit for a voice coil motor (VCM) includes a full bridge output stage for driving the motor in a pulse width modulated (PWM) mode. A multiplexer having two inputs is coupled to respective output nodes of the full bridge output stage, with one of the output nodes providing a back electromotive force induced in the motor upon setting in a high impedance state the full bridge output stage and conducting at least one transistor connected to ground in the full bridge output stage after current through the motor has decayed to zero. A controller compares a voltage representing a desired speed of the motor with the back electromotive force, and generates a correction signal based upon the comparison.

Abstract: Process of manufacturing a semiconductor device comprising a step of forming recessed zones in a semiconductor layer of a first conductivity type, a step of oxidation for forming a gate oxide layer at the sidewalls of the recessed zones, a step of forming a polysilicon gate electrode inside the recessed zones, a step of forming body regions of a second conductivity type in the semiconductor layer between the recessed zones, and a step of forming source regions of the first conductivity type in the body regions. The step of forming recessed zones comprises a step of local oxidation of the surface of the semiconductor layer wherein the recessed zones will be formed, with an oxide growth at the semiconductor layer's cost in order to obtain thick oxide regions penetrating in the semiconductor layer, and a step of etching wherein the oxide of the thick oxide regions is removed.

Abstract: A method of reading and restoring data stored in a ferroelectric memory cell is disclosed. The cell includes a first transistor and first ferroelectric capacitor connected, in series with each other, between a first bitline and an auxiliary line, a second transistor and second ferroelectric capacitor connected, in series with each other, between a second bitline and the auxiliary line, the first and second transistors having respective control terminals connected to a common wordline. The reading method includes precharging the first and second capacitors, applying a read pulse to the cell such that the state of the first capacitor is changed, reading the cell by a sensing means, and restoring the first capacitor to an initial state.

Abstract: An electronic power device is integrated monolithically in a semiconductor substrate. The device has a first power region and a second region, each region comprising at least one P/N junction formed of a first semiconductor region with a first type of conductivity, which first semiconductor region extends through the substrate from the top surface of the device and is diffused into a second semiconductor region with the opposite conductivity from the first. The device also includes an interface structure between the two regions, of substantial thickness and limited planar size, comprising at least one trench filled with dielectric material.

Abstract: Described herein is an output buffer including an output stage formed by a pull-up transistor and a pull-down transistor connected in series between a supply line set at a supply potential and a ground line set at a ground potential. The output buffer further including a pre-biasing stage for pre-biasing the control terminal of the pull-up transistor and a pre-biasing stage for pre-biasing the control terminal of the pull-down transistor in order to bring these transistors to the turning-on threshold.

Abstract: An integrated device based upon semiconductor technology, in particular a chemical microreactor, including a semiconductor body having a high-temperature operating portion and a low-temperature operating portion. The semiconductor body is provided with a thermal-insulation device including a dissipator element arranged between the high-temperature operating portion and the low-temperature operating portion. The dissipator includes a membrane connecting the high-temperature operating portion and the low-temperature operating portion, and a plurality of diaphragms that extend substantially orthogonal to the membrane and are parallel to one another.

Abstract: An integrated electronic circuit includes a plurality of active circuits connected together in cascade. A feedback loop is between an output of a last active circuit and an input of a first active circuit so that the plurality of active devices function as a non-linear device, such as an inductor. The integrated electronic circuit may be integrated or used in association with a circuit network including other non-linear devices.

Abstract: A process for fabricating non-volatile memory cells on a semiconductor substrate includes forming a stack structure comprised of a first polysilicon layer isolated from the substrate by an oxide layer. The first polysilicon layer, oxide layer, and semiconductor substrate are cascade etched to define a first portion of a floating gate region of the cell and at least one trench bordering an active area of the memory cell. The at least one trench is filled with an isolation layer. The process further includes depositing a second polysilicon layer onto the whole exposed surface of the semiconductor, and etching the second polysilicon layer to expose the floating gate region formed in the first polysilicon layer, thereby forming extensions adjacent the above portion of the first polysilicon layer.

Abstract: An LDMOS structure is formed in a region of a first type of conductivity of a semiconductor substrate and comprises a gate, a drain region and a source region. The source region is formed by a body diffusion of a second type of conductivity within the first region, and a source diffusion of the first type of conductivity is within the body diffusion. An electrical connection diffusion of the second type of conductivity is a limited area of the source region, and extends through the source diffusion and reaches down to the body diffusion. At least one source contact is on the source diffusion and the electrical connection diffusion. The LDMOS structure further comprises a layer of silicide over the whole area of the source region short-circuiting the source diffusion and the electrical connection diffusion. The source contact is formed on the silicide layer.

Abstract: The invention relates to a process for manufacturing a light sensor device in a standard CMOS process, including, implanting active areas on a semiconductor substrate to obtain a first integrated region of a corresponding photosensor; and forming a stack of layers having different thickness and refractive index layers over the photosensor to provide interferential filters for the same photosensor. At least one of the above mentioned layers is formed by a transparent metallic oxide having a high refraction index and a corresponding high dielectric constant. In this manner, due to the transparency of the high refraction index material, the design of interferential resonators is rendered more flexible making possible the use of a stack of layers including more than one high refraction index layer.

Abstract: A method for simulating an integrated circuit includes dividing the integrated circuit into a plurality of independent subcircuits using a digital simulator, electrically simulating each of the independent subcircuits for a simulation result, and linking together the simulation results. By splitting the simulation of the integrated circuit into a plurality of simulations of smaller independent subcircuits, the electrical simulation is faster and can be performed in parallel since each subcircuit is independent.

Abstract: A circuit to control the supply of a reactive load, for supplying variable quantities of energy to the load in a predetermined manner is included in a system. The system also includes reactive components which are connected to the load by way of a controllable electronic switch and which form a resonant circuit with the load when the electronic switch is closed. Further, the system includes a circuit for activating the electronic switch, and a control unit which coordinates the operation of the controlled supply circuit and of the activation circuit in accordance with a predetermined program. The system enables the load to be driven with a particularly low power dissipated.

Abstract: A driver circuit drives at least one power switch, which circuit comprises a final stage including a complementary pair of power transistors connected to said switch at a common output node. Advantageously, this circuit comprises a respective power-on buffer stage, connected in upstream of each of the power transistors, and a power-on detector associated with each power transistor, the detector associated with one of the power transistors being connected to the buffer stage of the complementary one of the transistors to prevent the power transistors from being turned on simultaneously.