Abstract: A method for detecting displacements of a micro-electromechanical sensor including a fixed body and a mobile mass, and forming a first sensing capacitor and a second sensing capacitor having a common capacitance at rest. The first and second sensing capacitors being connected to a first input terminal and, respectively, to a first output terminal and to a second output terminal of the sensing circuit. The method includes the steps of closing a first negative-feedback loop, which is formed by the first and second sensing capacitors and by a differential amplifier, feeding an input of the differential amplifier with a staircase sensing voltage through driving capacitors so as to produce variations of an electrical driving quantity which are inversely proportional to the common sensing capacitance, and driving the sensor with the electrical driving quantity.

Abstract: A process for cleaning an integrated circuit package surface, comprising the steps of introducing the integrated circuit inside a plasma chamber; and of exposing the integrated circuit to a physical plasma obtained starting from a gas consisting of pure argon or any other noble gas having, in the plasma state, the behavior of a halogen, for example helium. The argon pla sma is obtained using the following energization parameters: energization time, 12-13 seconds; energization power, 140-160 W; plasma chamber pressure, 190-210 millitorr; and energization frequency, between 1 kHz and 100 GHz.

Abstract: A reading circuit is provided for reading a memory cell. The reading circuit includes a reference current source, a memory cell biased between its first and second terminals at a predetermined voltage, comparison means for comparing a current flowing in the memory cell with the reference current, and a control gate voltage source coupled to a third terminal of the memory cell. The control gate voltage source includes a virgin memory cell that is biased between two terminals with a voltage of equal value to the biasing voltage of the memory cell. The control gate voltage source produces a control gate voltage at another terminal of the virgin memory cell. In one preferred embodiment, the memory cell and the virgin memory cell are EEPROM cells.

Abstract: A receiver portion of a telephone includes a differential amplifier stage with a single output, an electroacoustic transducer connected between the output, via a capacitor and ground and a unit for controlling switching on/off, connected to the differential stage for the activation or deactivation thereof. To prevent annoying noises in the transducer upon switching on and off, the differential stage includes an operational amplifier having a first capacitor and a second capacitor in series with the inverting and the non-inverting input terminals. A third capacitor is connected between the inverting input and the output of the operational amplifier. A fourth capacitor is connected between the non-inverting input and a first reference-voltage terminal. A first switching capacitor is alternatively connectable between a second and a third reference-voltage terminal, or between the first input and the output of the operational amplifier.

Abstract: A switching control method for level shifter includes a phase of de-selection of a high voltage value at an output terminal of the shifter using a selection signal. The de-selection phase may include starting the de-selection by bringing the selection signal to a low value; de-activating by way of the selection signal, the generation of a high-voltage signal being supplied to the shifter, and a reference voltage signal; computing the difference between an internal voltage signal of the shifter and the reference voltage signal; generating a control signal when the difference is found to be less than a threshold voltage value; and applying the selection signal to an input terminal of the shifter in the presence of the control signal.

Abstract: The invention relates to a method of adjusting the erase/program voltage in semiconductor non-volatile memories. The memories are formed of at least one matrix of memory cells having a floating gate, a control gate, and drain and source terminals, and are organized by the byte in rows and columns, each byte comprising a group of cells having respective control gates connected in parallel with one another to a common control line through a selection element of the byte switch type, and each cell being connected to a respective control column through a selection element of the bit switch type. Advantageously, a double adjustment is provided for the program voltage of the memory cells, whereby the program voltage during the erasing phase can be higher in modulo than the program voltage during the writing phase.

Abstract: A current control method controls current for drive systems of multi-phase brushless motors, in particular at phase switching, wherein the motor coils coupled to a common node are driven by applying a respective drive voltage to the free end of each coil via corresponding power stages. The method comprises switching the current flow from one phase to the next in the direction of rotation of the motor at the phase switch, thereby forcing the unaffected one of said coils by the phase switch into a state of high impedance. Advantageously, the decreasing rate of the current in the coil unaffected by the phase switch can be twice as high as the decreasing rate of the current in the phase being switched from.

Abstract: The equivalent computational precision in an associative memory is increased by determining the difference between the bit precision that is required in order to represent a given number in the memory and the bit precision that can be represented in a memory element of the memory, which is dictated by the inherent characteristics of the memory; determining, on the basis of the difference, the number of memory elements of the memory required in order to represent the given number with the required bit precision; and dividing the given number over the number of memory element of the memory, determining a base value to be loaded into the number of memory element and a remainder which indicates a subset of the number of memory element of the memory over which the remainder is to be divided.

Abstract: A sensing circuit for sensing a memory cell, the sensing circuit having a first circuit branch electrically connectable to the memory cell to receive a memory cell current, the first circuit branch having at least one first transistor that, when the first circuit branch is connected to the memory cell, is coupled thereto substantially in a cascode configuration. A bias current generator is operatively associated with the first transistor for forcing a bias current to flow therethrough.

Abstract: Described herein is an output buffer including an output stage formed by a pull-up transistor and a pull-down transistor, which are connected in series between a supply line set at a supply potential and a ground line set at a ground potential, with an intermediate node connected to the output of the output buffer. The output buffer further includes a unidirectional decoupling stage arranged between the output of the output buffer and the pull-up transistor for decoupling the output from the supply line during the switching transients of the output buffer in such a way as to prevent the switching noise present on the latter from being transferred onto the output of the output buffer.

Abstract: A semiconductor memory such as a flash memory, which comprises at least one two-dimensional array of memory cells with a plurality of rows and columns of memory cells grouped in a plurality of packets. The memory cells belonging to the columns of each packet are formed in a respective semiconductor region with a first type of conductivity, this region being distinct from the semiconductor regions with the first type of conductivity in which the memory cells belonging to the columns of the remaining packets are formed. The semiconductor regions with the first type of conductivity divide the set of memory cells belonging to each row into a plurality of subsets of memory cells that constitute elemental memory units which can be modified individually. Thus memory units of very small dimensions can be erased individually, without excessive overhead in terms of area.

Abstract: A head (130) for a disk storage device having a plurality of tracks (117) divided into memory cells (234), including a magnetic circuit (205, 230a, 230b, 250a, 250b) for reading the memory cells (234) in succession, the magnetic circuit (205, 230a, 230b, 250a, 250b) for reading the memory cells (234) including at least two partial reading components (206a, 230a, 250a; 206b, 230b, 250b) each for reading a portion (234a; 234b) of each memory cell (234), the portions (234a; 234b) being arranged transversely relative to the longitudinal axis (233) of the corresponding track (117).

Abstract: An area-efficient reconstruction filter removes undesirable sample images produced by current-driven digital-to-analog converters. The reconstruction filter includes: an input node for receiving the input current signal; an operational amplifier having first and second inputs and an output at which the output voltage signal is produced; a first resistor coupled between the output of the operational amplifier and the input node; a second resistor coupled to the first input of the operational amplifier; and a third resistor coupled between the input node and the second resistor. The reconstruction filter may also include a fourth resistor coupled between the input node and a reference voltage.

Abstract: A bi-dimensional position sensor that can be advantageously used in the turn system controlled from the steering wheel of a vehicle. The sensor includes a permanent magnet fixed to a control lever so as to move in a plane along first and second directions and to rotate about a third direction orthogonal to the preceding ones. The permanent magnet is movable with respect to an integrated device including a first group of sensor elements arranged spaced along the first direction, a second group of sensor elements arranged spaced along the second direction and a third group of sensor elements detecting the angular position of the permanent magnet. Electronics integrated with the sensor elements generate a code associated with each position which the permanent magnet may assume and generate a control signal corresponding to the desired function.

Abstract: A method of making an integrated circuit that is resistant to an unauthorized duplication through reverse engineering includes forming a plurality of false contacts and/or false interconnection vias in the integrated circuit. These false contacts and/or false interconnection vias are connected as true contacts and true interconnection vias by lines patterned in a metallization layer deposited over an insulating dielectric layer or multilayer through which the true contacts and/or the true interconnection vias are formed. False contacts and false vias extend in the respective dielectric layers or multilayers to a depth insufficient to reach the active areas of a semiconductor substrate for false contacts, or to a depth insufficient to reach a layer of conductive material below the dielectric layers or multilayers for false interconnection vias.

Abstract: A method corrects the errors in a multilevel memory, by increasing the number of levels of the memory cells, instead of adding further memory cells. In other words, the present correction method is based on the principle of storing, in each multilevel memory cell, instead of a whole number b of bits in the binary word to be stored, data units which are correlated to this binary word, and are expressed in a numerical base other than binary, and not a power of two. This is carried out by converting the binary word with m bits to be stored, from the binary base, to a base n, which is not a power of two, and by associating with the converted word a correction word, which is also formed from digits with a base n; the digits of the converted and correction words are then each stored in a respective multilevel memory cell, with a number of levels which is equivalent to the numerical base used for the conversion.

Abstract: A device for generating synchronous numeric signals, including a first signal generator which supplies a numeric reference signal having a first frequency and a first period; and a second signal generator which generates an internal numeric signal having a second frequency and a second period, and a synchronized numeric signal. In addition, the second signal generator includes a predictor which generates, with a third period and a third frequency higher than the first frequency and the second frequency, estimated samples correlated to a current sample and to a predetermined number of former samples of the internal numeric signal. The predictor, in turn, includes a selection circuit controlled by the first signal generator for selecting one among the estimated samples in each reference period, the synchronized numeric signal being formed by the selected estimated samples.

Abstract: A method of producing a protective inhibitor layer of moisture-generated corrosion for aluminum (Al) alloy metallization layers, particularly in semiconductor electronic devices, includes chemically treating the metallization layer in at least two steps using a mixture of concentrated nitric acid and trace phosphoric acid to produce a thin protective phosphate layer. Alternatively, the method may include dipping the electronic device at least once in a mixture of a polar organic solvent and phosphoric acid (H3PO4) or phosphate derivatives thereof in a low percentage amount (e.g., with a phosphate reactant such as orthophosphoric acid or even R—HxPOy, where R is an alkaline type of ion group or an alkyl radical). The thin film may be formed on top of a thin layer of native aluminum oxide hydrate Al2O3.xH2O.

Abstract: An electronic device having first and second external pins; first and second pads connected to the first external pin by respective bonding wires; and third and fourth pads connected to the second external pin respective bonding wires, and to a first common line by respective resistors. By means of a circuit configuration of this type, the intactness of the bonding wires can easily be checked by carrying out a simple resistance measurement between the first and the second external pin.

Abstract: A modular semiconductor power device has a conductive member consisting of an alumina plate to which copper layers are soldered on opposite sides. A chip is soldered to one of these layers and the other of these layers is soldered in turn to a metal heat sink. The chip is connected to respective copper strips which, in turn, are soldered to thermal strips originally forming part of a frame so that, after the device is encapsulated in a synthetic resin, the connecting members of the frame can be cut away to leave free ends of the latter strips exposed.