Abstract: A voltage follower includes a follower stage including first and second bipolar junction transistors connected in cascade, and a first current generator connected to the follower stage for biasing the first and second bipolar junction transistors. A cascode stage is connected between the first current generator and the first bipolar junction transistor, and a second current generator is connected between the first bipolar junction transistor and a first voltage reference. The voltage follower dissipates less power when the output current is small.

Abstract: A circuit device structured to enable a hierarchic form of row decoding in semiconductor memory devices of the non-volatile type and including a matrix of memory cells with sectors organized into columns, wherein each sector has a group of local word lines individually connected to a main word line running through all of the matrix sectors which have rows in common is presented. The device includes a PMOS first transistor having conduction terminals connected respectively to the main word line and the local word line, an NMOS second transistor having conduction terminals connected respectively to the local word line and the main word line, and a PMOS third transistor having conduction terminals connected respectively to the main word line and the local word line. Such a third transistor is a charge transistor that reduces the charging time for the local word line.

Abstract: An inkjet print head includes an ink drop emission mini-gun and a drop emission sensor integrated in a chip of semiconductor material. The mini-gun is formed by an ink chamber and a nozzle in communication with the ink chamber and the drop emission sensor includes a resistive element arranged in a position adjacent to the ink chamber. The resistance of the resistive element depends on the pressure exerted thereon, so that when the mini-gun emits an ink drop, it is subjected to a recoil movement which causes a change of pressure and hence of resistance in the resistive element; this change in resistance may be detected through suitable circuitry to identify whether and when a drop of ink has been emitted.

Abstract: A circuit structure for semiconductor devices which are integrated on a semiconductor layer is provided. The structure comprises at least one MOS device and at least one capacitor element that has a bottom and a top electrode. The MOS device has conduction terminals formed in the semiconductor layer, as well as a control terminal covered with an overlying insulating layer of unreflowed oxide. The capacitor element is formed on the unreflowed oxide layer.

Abstract: A portable system carried by a user for assessing movement of the user includes at least one motion sensor adjacent a portion of the user's body under observation. An analog-to-digital converter is connected to the motion sensor for converting an analog signal therefrom into a digital signal. A logic circuit is connected to the analog-to-digital converter for calculating parameters based upon the digital signal. A first fuzzy logic processing circuit is connected to the logic circuit for processing the calculated parameters and for generating corresponding fuzzy classification labels based upon movement of the portion of the user's body under observation during an interval of time. A memory is connected to the first fuzzy logic processing circuit for storing at least one of the calculated parameters and the fuzzy classification labels.

Abstract: A word recognition device uses an associative memory to store a plurality of coded words in such a way that a weight is associated with each character of the alphabet of the stored words, wherein equal weights correspond to equal characters. To perform the recognition, a dictionary of words is first chosen; this is stored in the associative memory according to a pre-determined code; a string of characters which correspond to a word to be recognized is received; a sequence of weights corresponding to the string of characters received is supplied to the associative memory; the distance between the word to be recognized and at least some of the stored words is calculated in parallel as the sum of the difference between the weights of each character of the word to be recognized and the weights of each character of the stored words; the minimum distance is identified; and the word stored in the associative memory having the minimum distance is stored.

Abstract: A circuit for driving capacitive loads in a highly efficient manner. In one embodiment, a drive portion is connected to at least one end of a capacitive electric load being applied a voltage waveform. The embodiment further comprises a switching circuit portion having its output connected to the above one end of the capacitive load in order to supply a fraction of the overall current demanded by the load. Additionally, a switching circuit and accompanying switching method provide for efficiently supplying peak current to the capacitive load during voltage fluctuation in the voltage waveform. Briefly, the invention is a circuit arrangement aimed at providing a highly efficient drive for the capacitive load, using a combined linear/switching setup and without distorting the quality of the waveform generated across the capacitive load.

Abstract: A power-on reset circuit connected to a supply line feeding a supply voltage, the circuit including an output terminal supplying a power-on reset signal; a divider connected between the supply line (36) and ground and having an intermediate node supplying a division voltage correlated to the supply voltage; an inverter having an input connected to the intermediate node and an output connected to the output terminal and supplying a reset logic signal; and a deactivation branch coupled to the supply line and the intermediate node. The deactivation branch preventing switching of the power-on reset signal on the output terminal when the supply voltage is higher than a deactivation voltage.

Abstract: A microelectromechanical structure includes a rotor element having a barycentric axis and suspended regions arranged a distance with respect to the barycentric axis. The rotor element is supported and biased via a suspension structure having a single anchoring portion extending along the barycentric axis. The single anchoring portion is integral with a body of semiconductor material on which electric connections are formed.

Abstract: A Switched Reluctance Motor or SRM is controlled by detecting signals indicating the angular position of the rotor of the motor and energizing the motor depending on these signals. The periods of the abovementioned signals are discretized into a given number of time windows, defining a table with a plurality of positions each corresponding to one of said time windows. A respective power supply configuration of the motor is associated with each of said positions of the table. The positions in the table undergo cyclical scanning and the motor is energized with the power supply configuration associated with the position identified in each case during the scanning movement. The scanning movement is performed from a reference position identifying the energization advance of the motor and preferably determined using a logic of the fuzzy type based on the speed of rotation and the load of the said motor.

Abstract: A process for the manufacturing of electronic devices, including memory cells, involving forming, on a substrate of semiconductor material, multilayer stacks including a floating gate region, an intermediate dielectric region, and a control gate region; forming a protective layer extending on top of the substrate and between the multilayer stacks and having a height at least equal to the multilayer stacks. The step of forming multilayer stacks includes the step of defining the control gate region on all sides so that each control gate region is completely separate from adjacent control gate regions. The protective layer isolates the multilayer stacks from each other at the sides. Word lines of metal extend above the protective layer and are in electrical contact with the gate regions.

Abstract: A method for fabricating a silicon-on-insulator (SOI) wafer that includes a monocrystalline silicon substrate with a doped region buried therein is provided. The method includes forming a plurality of trench-like openings extending from a surface of the substrate to the doped buried region, and selectively etching through the plurality of trench-like openings to change the doped buried region into a porous silicon region. The porous silicon region is oxidized to obtain an insulating region for the SOI wafer.

Abstract: The device and method monitor the current delivered to a load through a power transistor including a sense transistor. The circuit includes a disturbances attenuating circuit that has a differential stage, and first, second and third stages referenced to ground, the respective input nodes of which are connected in common to an output node of the differential stage. The third stage is formed by a transistor identical to a transistor of the first stage and delivers a current signal through a current terminal thereof, proportional to the current being delivered to the load.

Abstract: A method for providing an SOI wafer that includes, on a wafer of monocrystalline semiconductor material, forming a hard mask of an oxidation-resistant material, defining first protective regions covering first portions of the wafer; excavating the second portions of the wafer, forming initial trenches extending between the first portions of the wafer; thermally oxidating the wafer, forming a sacrificial oxide layer extending at the lateral and base walls of the initial trenches, below the first protective regions; and wet etching the wafer, to completely remove the sacrificial oxide layer. Thereby, intermediate trenches are formed, the lateral walls of which are recessed with respect to the first protective regions. Subsequently, a second oxide layer is formed inside the intermediate trenches; a second silicon nitride layer is deposited; final trenches are produced; a buried oxide region is formed, and finally an epitaxial layer is grown.

Abstract: A circuit structure for programming data in reference cells of an electrically programmable/erasable integrated non-volatile memory device includes a matrix of multi-level memory cells and a corresponding reference cell provided for comparison with a respective memory cell during the read phase. The reference cell is incorporated, along with other cells of the same type, in a reference cell sub-matrix which is structurally independent of the memory cell matrix and directly accessed from outside in the DMA mode. The bit lines of the sub-matrix branch off to a series of switches which are individually operated by respective control signals REF(i) issued from a logic circuit with the purpose of selectively connecting the bit lines to a single external I/O terminal through a single addressing line of the access DMA mode.

Abstract: Presented is an analog voltage value measuring device for measuring any of a set of voltage references that are generated inside a memory architecture. The selected voltage to be measured is connected to a facility line through a multiplexer. The memory architecture includes a set of output buffers connected to a respective set of output pads. The device also includes a converter block, connected between the facility line and the output buffers of the memory architecture for converting a measured analog value of a voltage reference selected by the multiplexer to a digital value, which is presented on the output pads. A method of measuring an analog voltage value in a memory device is also disclosed. The method includes selecting an analog voltage value from the set of voltage values; transferring the selected analog value onto the facility line; converting the selected analog value to a digital value; and presenting the digital value on the output pads.

Abstract: An integrated self-powered and switching electronic circuit regulates a stable reference voltage and comprises a band-gap voltage generator to produce said stable reference voltage for a system circuit block that is generally supplied by the output of the band-gap generator through a comparator and an error amplifier. A regulating loop is provided between the output of the system block and the input of the voltage generator circuit to supply a voltage signal produced by the output of the system block. Advantageously, the voltage generator circuit incorporates both the comparator and the error amplifier.

Abstract: A flash EEPROM having an array of memory cells which include a common source line connecting together source electrodes of the memory cells. A resistive feedback element is coupled in series between the common source line and a positive potential when the memory cells must be electrically erased. The Flash EEPROM includes a voltage limiting circuit coupled to the common source line for limiting the potential of the common source line to be prescribed maximum value lower than the positive potential.

Abstract: A column decoder circuit for page reading of a semiconductor memory includes a first level decoder stage, a second level decoder stage, and a plurality of bit selection stages, each comprising a plurality of selection branches; wherein each selection branch is connected to a respective input of a multiplexer and has a plurality of first level selector stages and a second level selector stage. Each second level selector stage comprises a first addressing selector for addressing a first group of bit lines. Each bit selection stage further comprises a second addressing selector for addressing a second group of bit lines, current and next page selectors for selecting one of the first and second groups of bit lines.

Abstract: A method manages lamp fault conditions in electronic ballasts for one or more gas discharge lamps. The method for fault management of electronic ballast for at least one gas discharge lamp includes the steps of: preheating the lamp filaments applying a low current for a predetermined time; igniting the lamp by increasing at a predetermined rate the voltage applied up to a predetermined strike value; monitoring the lamp current; repeating the steps of igniting the lamp and monitoring the lamp current for a predetermined numbers of times if the lamp current is over a predetermined threshold; and powering the lamp at normal operating conditions.