Abstract: A driving circuit of a DC motor includes a control circuit for providing a control signal, and a motor drive circuit commanded by the control circuit for providing respective command signals for the switches of an output power stage connected to the DC motor. The output power stage is connected to a power supply line and drives the windings of the DC motor. The driving circuit prevents generation of voltage surges having a significant magnitude on the power supply line because the driving circuit has logic circuits for preventing any substantial inversion in the direction of current flow in the supply lines when the DC motor operates as a current generator.

Abstract: A power device with integrated voltage stabilizing circuit, comprising a MOS transistor that is connected in parallel to a circuit that is integrated in a power device, at least one Zener diode with a series-connected resistor being connected in parallel to the transistor, the gate terminal of the transistor being connected to an intermediate node between the Zener diode and the resistor, the anode terminal of the Zener diode and the drain terminal of the transistor being connected to an input voltage of the circuit.

Abstract: A method for manufacturing integrated capacitive elements on a semiconductor substrate includes depositing a first metallization layer on a first dielectric layer. The first metallization layer includes a lower plate for a capacitive element and an interconnection pad. The method further includes forming a second dielectric layer over the first dielectric layer, forming a first opening aligned with the lower plate through the second dielectric layer, and depositing a third dielectric layer on the second dielectric layer and the lower plate and covering sidewalls of the first opening. A second opening is formed through the third dielectric layer and aligned with the interconnection pad. A fourth dielectric layer is deposited on the whole wafer surface, wherein the fourth dielectric layer is etchable in a completely selective manner relative to the third dielectric layer.

Abstract: An electric connection structure connecting a first silicon body to conductive regions provided on the surface of a second silicon body arranged on the first body. The electric connection structure includes at least one plug region of silicon, which extends through the second body; at least one insulation region laterally surrounding the plug region; and at least one conductive electromechanical connection region arranged between the first body and the second body, and in electrical contact with the plug region and with conductive regions of the first body. To form the plug region, trenches are dug in a first wafer and are filled, at least partially, with insulating material. The plug region is fixed to a metal region provided on a second wafer, by performing a low-temperature heat treatment which causes a chemical reaction between the metal and the silicon. The first wafer is thinned until the trenches and electrical connections are formed on the free face of the first wafer.

Abstract: Described herein is a nonvolatile memory comprising a memory array organized according to global word lines and local word lines; a global row decoder; a local row decoder; a first supply stage for supplying the global row decoder; and a second supply stage for supplying the local row decoder; and a third supply stage for biasing the drain and source terminals of the memory cells of the memory array. Each of the supply stages comprises a respective resistive divider formed by a plurality of series-connected resistors, and a plurality of pass-gate CMOS switches each connected in parallel to a respective resistor. The nonvolatile memory further comprises a control circuit for controlling the pass-gate CMOS switches of the supply stages, and a switching circuit for selectively connecting the supply input of the control circuit to the output of the second supply stage during reading and programming of the memory, and to the output of the third supply stage during erasing of the memory.

Abstract: A processor is provided with a set of instructions formed, in general, of an operation section and an operand section. For a special control instruction, the operand section is transmitted to the operation blocks along a bypass path separate from the normal path in which normal instructions are interpreted. In this way, an extension of the set of instructions can be achieved for tailoring the set of instructions to the user's own requirements. Consequently, the processor control unit should be capable of coupling its outputs to its inputs upon receiving one such instruction, thereby to transfer such internal operation control signals without interpretation.

Abstract: A method for forming isolating structures in a silicon carbide layer includes depositing a masking layer on first and second portions of the silicon carbide layer, and forming openings through the masking layer to expose the first portions of the silicon carbide layer. Ions are implanted into the first portions of the silicon carbide layer. The silicon carbide layer is heated to form an oxide layer thereon having first portions on the first portions of the silicon carbide layer, and having second portions on the second portions of the silicon carbide layer. The first portions of the oxide layer are etched to form isolating regions in the silicon carbide layer.

Abstract: In an actuator device for hard disks a suspension element carries a slider that is subject to undesired vibrations which give rise to rotations of the slider with respect to a nominal position. An electrostatically controlled position-control structure is arranged between the suspension and the slider and is controlled in an active way so as to generate torsions of the platform that counter the undesired rotations. The position-control structure comprises a platform of conductive material and control electrodes arranged underneath the platform. The platform is connected to a load-bearing structure by spring elements that enable movements of roll and pitch. Four control electrodes are arranged according to the quadrants of a square and can be selectively biased for generating electrical forces acting on the platform.

Abstract: A fuel cell for an electrical load circuit includes a first monocrystalline silicon substrate and a positive half-cell formed therein, and a second monocrystalline silicon substrate and a positive half-cell formed therein. Each half-cell includes a microporous catalytic electrode permeable to a gas and connectable to the electrical load circuit. A cell area is defined on a surface of each respective monocrystalline silicon substrate, and includes a plurality of parallel trenches formed therein for receiving the gas to be fed to the respective microporous catalytic electrode. A cation exchange membrane separates the two microporous catalytic electrodes. Each half-cell includes a passageway for feeding the respective gas to the corresponding microporous catalytic electrode.

Abstract: A process for manufacturing an electronic device having an HV MOS transistor with a low multiplication coefficient and a high threshold in a non-implanted area of the substrate, this area having the same conductivity type and the same doping level as the substrate. The transistor is obtained by forming, over the non-implanted substrate area, a first gate region of semiconductor material having the same doping type as the non-implanted substrate area; and forming, inside the non-implanted substrate area, first source and drain regions of a second conductivity type, arranged at the sides of the first gate region. At the same time, a dual-gate HV MOS transistor is formed, the source and drain regions of which are housed in a tub formed in the substrate and having the first conductivity type, but at a higher concentration than the non-implanted substrate area. It is moreover possible to form a nonvolatile memory cell simultaneously in a second tub of the substrate of semiconductor material.

Abstract: An internal addressing structure for a semiconductor memory with at least two memory banks, includes a counter associated for operation with each memory bank and capable of generating sequences of digital codes for addressing locations in the corresponding bank, a first circuit for causing a selective updating of the counters, a second circuit for loading into the counters a common initial digital code, forming part of an initial address supplied to the memory from the outside through an addressing line bus, corresponding to an initial memory location, and a third circuit capable of detecting a first signal, supplied to the memory from the outside and indicating the presence of a digital code on the bus, to cause the common initial digital code to be loaded into the counters.

Abstract: The present invention relates a circuit arrangement for the lowering of the threshold voltage of a diode configured transistor comprising a mirror transistor, a first transistor and a second transistor, said mirror transistor and said first transistor having in common the gate electrodes in a circuit node, said second transistor being connected in a transdiode configuration and placed between the gate electrode and the drain electrode of said first transistor, and a current source being connected to the gate electrode of said first transistor and to the drain electrode of said second transistor, characterized by comprising a third transistor which is configured to receive a switching signal at its gate electrode and is connected between the drain and the gate electrode of said first transistor.

Abstract: A microactuator is attached to a first face of a coupling formed on a suspension, so that an R/W transducer projects from an opposite face. A hole in the coupling permits passage of an adhesive mass interposed between a rotor of the microactuator and the R/W transducer. A strip of adhesive material extends between a die accommodating the microactuator and the coupling, and externally surrounds the microactuator. The coupling acts as a protective shield for the microactuator, both mechanically and electrically. The coupling covers the microactuator at the front, and prevents foreign particles from blocking the microactuator. In addition, the coupling electrically insulates the R/W transducer, which is sensitive to magnetic fields, from regions of the microactuator biased to a high voltage. With the coupling, the strip forms a sealing structure, which in practice surrounds the microactuator on all sides.

Abstract: A digital decimation filter includes a set of cascaded integrator stages for generating a first signal comprised of bit words including a first number of bits as well as a set of cascaded derivative stages for receiving said first signal and generating therefrom an output comprised of bit words including a second number of bits. The second number of bits is smaller than said first number of bits and a bit discarding unit is located downstream of the integrator stages and upstream of the derivative stages for discarding a given number of least significant bits from the bit words of the first signal before this is received by the derivative stages. Said given number is defined as the difference between said first and said second number of bits.

Abstract: The column multiplexer is for a memory matrix having memory cells arranged in rows and columns. The multiplexer includes input lines for input signals, a plurality of output lines for electrical connection to the columns of the matrix, a selective connection device for selecting, in a first operation mode, at least one output line of the plurality of output lines in such a way as to connect it selectively to the input lines. In the first operation mode, the selective connection device selects a first group of output lines among the plurality of output lines, including at least three first lines.

Abstract: An analog-to-digital conversion method and device for a multilevel non-volatile memory devicethat includes a multilevel memory cell. The method comprises a first step of converting the most significant bits contained in the memory cell, followed by a second step of converting the least significant bits. The first step is completed within a time interval corresponding to the rise transient of the gate voltage, and the second step is initiated at the end of the transient. Also disclosed is a scheme for error control coding in multilevel Flash memories. The n bits stored in a single memory cell are organized in different “bit-layers”, which are independent from one another. Error correction is carried out separately for each bit-layer. The correction of any failure in a single memory cell is achieved by using a simple error control code providing single-bit correction, regardless of the number of bits stored in a single cell.

Abstract: A memory system includes a memory matrix formed on a semiconductor structure. The memory matrix includes a first column line and a second column line which are connected electrically to at least one first memory cell to be read. For the reading of the at least one first cell, a first reading voltage can be supplied to the first column line. The memory matrix also includes a third column line distinct from the first column line and from the second column line. The memory matrix further includes generating circuit for supplying, to the third column line and during the reading of the at least one first memory cell, a biasing voltage which can oppose the establishment of an electric current between the first column line and the third column line in the semiconductor structure. The biasing voltage is preferably substantially equal to the first reading voltage.

Abstract: A DC-DC converter may comprise a plurality of voltage multiplying stages of the capacitive type, each multiplying stage comprising a plurality of selectively connectable boosting branches. In one embodiment, the DC-DC converter comprises an inductor connected between a supply line and a ground line through a switching transistor; a voltage multiplying circuit formed by a plurality of voltage multiplying stages of capacitive type, connected together in cascade and each having an input connected to an intermediate node between the inductor and the transistor, and an output supplying a potential equal to the potential of the intermediate node multiplied by a respective multiplication factor. Each voltage multiplying stage comprises a plurality of parallel, selectively connectable boosting branches. The number of the active boosting branches may be varied in response to the energy required by the loads.

Abstract: A successive-approximation analog-digital converter including a logic control circuit timed by means of an external clock signal clock. The logic control circuit includes a register containing a first digital signal formed of N bits, which is the product of a first analog-digital conversion. The logic control circuit is suitable for producing a second digital signal formed of N bits through a second analog-digital conversion in N clock cycles. This analog-digital converter converts the second digital signal sent by the logic circuit to a second analog signal. A comparator compares the first analog signal with the second analog signal which has been input to the analog-digital converter.

Abstract: A method is provided for manufacturing electronic non-volatile memory devices on a semiconductor substrate including a matrix of memory cells having floating gate regions formed on respective active areas and an oxide layer separating the active areas. The method may include forming sidewalls of the floating gate regions that are slanted with respect to a surface of the semiconductor substrate, forming a trench in the oxide layer following the formation of the floating gate regions, and forming a plug of polycrystalline silicon in the trench. The slanted sidewalls of the floating gate regions provide a leading for the formation of upper layers.