Abstract: Abstract of the Disclosure A monolithically integrated pressure sensor is produced through micromechanical surface structure definition techniques. A microphone cavity in the semiconductor substrate may be monolithically formed by plasma etching the front side or the back side of the silicon wafer to cut a plurality of trenches or holes deep enough to extend for at least part of its thickness into a doped buried layer of opposite type of conductivity of the substrate and of the epitaxial layer grown over it. The method may also include electrochemically etching through such trenches, the silicon of the buried layer with an electrolytic solution suitable for selectively etching the doped silicon of the opposite type of conductivity, thereby making the silicon of the buried layer porous. The method may also include oxidizing and leaching away the silicon so made porous.

Abstract: The method for reading a memory cell is based upon integration in time of the current supplied to the memory cell by a capacitive element. The capacitive element is initially charged and then discharged linearly in a preset time, while the memory cell is biased at a constant voltage. In a first operating mode, initially a first capacitor and a second capacitor are respectively charged to a first charge value and to a second charge value. The second capacitor is discharged through the memory cell at a constant current in a preset time; the first charge is shared between the first capacitor and the second capacitor; and then the shared charge is measured.

Abstract: A circuit estimates speed of an electromagnetic actuator associated with a reading head of a disk storage unit and a digital controller. The circuit includes first and second supply terminals and an output terminal, with the first supply terminal being connected to the electromagnetic actuator. A measuring resistor is connected to the second supply terminal, and is connected in series with the electromagnetic actuator for measuring a current which passes therethrough when a supply voltage is applied between the first and second supply terminals. An adder has an output connected to the output terminal for providing an output voltage, a first input is connected to the first supply terminal, and a second input is connected to the second supply terminal. An adjustable-gain amplifier is connected between the measuring resistor and the second input of the adder for transferring the supply voltage and a voltage across the measuring resistor to the adder.

Abstract: A sense amplifier of the type coupled to a reference bit line and at least one cell array bit line. The sense amplifier includes an amplifying stage and a current voltage conversion circuit that compare a reference current from the reference bit line and a cell current from the cell array bit line. The current-voltage conversion circuit includes a voltage setting circuit for setting predetermined voltages on the reference bit line and the cell array bit line, a load circuit for the reference bit line and the cell array bit line, and current mirror circuits for mirroring the reference current and the cell current into the amplifying stage. The load circuit for the reference bit line and the current mirror circuit for the reference current are different circuits, and the load circuit for the reference bit line includes a transistor that mirrors a predetermined current that is generated outside of the sense amplifier.

Abstract: A chip of semiconductor material includes a first layer with a first type of conductivity having a surface on the first major surface of the chip, a second layer with the first type of conductivity having a surface on the second major surface of the chip, and a third layer with the first type of conductivity having a resistivity lower than those of the first and second layers and disposed between the first layer and the second layer. A first region with a second, type of conductivity, extends from the first surface into the first layer, and a second region with the second type of conductivity, extends from the second major surface into the second layer. First, second and third electrical connections are provided for connection with the first region, the second region, and the third layer, respectively.

Abstract: A non-volatile memory matrix architecture, having a virtual ground monolithically integrated on a semiconductor substrate, includes a plurality of memory cells organized into matrix blocks. The matrix blocks are placed on rows and columns and are associated with respective row and column decoding circuits. The memory blocks are separated from each other by at least one insulation stripe which is parallel to the columns. The non-volatile memory matrix architecture further includes a pass-transistor decoding circuit with a number of levels corresponding to the number of rows to select.

Abstract: A phase locked loop is provided that includes a phase comparator, a charge pump circuit, a loop filter, and a voltage controlled oscillator. The charge pump circuit includes two symmetric branches, feedback paths, and circuit breaking switches. Each of the symmetric branches has a constant current generator and a pulsed current generator, with one terminal of the loop filter being connected to one of the symmetric branches and the other terminal of the loop filter being connected to the other of the symmetric branches. The feedback paths control the constant current generators based on voltages at the terminals of the loop filter, and each of the circuit breaking switches couple one of the pulsed current generators and the corresponding terminal of the loop filter. The pulsed current generators supply a first current whose amplitude is proportional to an amplitude of a second current supplied by the constant current generators through the duty cycle of the first current.

Abstract: The device comprises a current mirror circuit having a first and a second node connected, respectively, to a constant current source and to a drain terminal of a memory cell to be programmed. A voltage generating circuit is connected to the first node to bias it at a constant reference voltage (VR); an operational amplifier has an inverting input connected to the first node, a non-inverting input connected to the second node, and an output connected to the control terminal of the memory cell. Thereby, the drain terminal of the memory cell is biased at the constant reference voltage, having a value sufficient for programming, and the operational amplifier and the memory cell form a negative feedback loop that supplies, on the control terminal of the memory cell, a ramp voltage (VPCX) that causes writing of the memory cell. The ramp voltage increases with the same speed as the threshold voltage and can thus be used to know when the desired threshold value is reached, and thus when programming must be stopped.

Abstract: An SMPS converter with an inductor connected in series to the standard inductor present in the output filter to form an inductive divider supplying an intermediate voltage having an amplitude greater than the output voltage. The intermediate voltage is supplied to a capacitor that stores the voltage during the conduction phase of the integrated circuit that forms the switch of the converter and transfers the voltage during opening of the integrated circuit to a capacitor connected between the output and the supply input of the integrated circuit.

Abstract: An integration process in a SOI substrate of a semiconductor device having at least a dielectrically insulated well, the process including: an oxidizing step directed to form an oxide layer; a depositing step of a nitride layer onto the oxide layer; a masking step, carried out onto the nitride layer using a resist layer and directed to define suitable photolithographic openings for forming at least one dielectric trench effective to provide side insulation for the well; an etching step of the nitride layer and oxide layer, as suitably masked by the resist layer, the nitride layer being used as a hardmask; a step of forming the at least one dielectric trench, which step comprises at least one step of etching the substrate, an oxidizing step of at least sidewalls of the at least one dielectric trench, and a step of filling the at least one trench with a filling material; and a step of defining active areas of components to be integrated in the well, being carried out after the step of forming the at least one d

Abstract: A thermal control circuit for an integrated power transistor includes a current generator controlled by a turn on signal, a sensing resistance in series with the power transistor, and a current limiter acting when the voltage drop on the sensing resistance overcomes a certain value. The circuit also includes a current amplifier coupled to the output node of the controlled current generator for outputting a drive current that is injected onto a control node of the power transistor. A soft thermal shut down circuit is provided having a conduction state which is enhanced as the temperature increases for reducing the drive current. The circuit controls the voltage on the power transistor in a more effective manner because the current amplifier has a variable gain controlled by the state of conduction of the soft thermal shut down circuit.

Abstract: Chip Outline Band (COB) structure for an integrated circuit integrated in a semiconductor chip having a semiconductor substrate of a first conductivity type and biased at a common reference potential of the integrated circuit, the COB structure comprising a substantially annular region formed in the substrate along a periphery thereof, and at least one annular conductor region superimposed on and contacting the substantially annular region, wherein the substantially annular region is electrically connected at the common reference potential.

Abstract: A system for diagnosing a driver and detecting circuit anomalies therein includes: voltage comparator circuits for generating diagnostic logic signals, each of which indicates the existence of a corresponding type of anomaly; and a coding circuit to receive the diagnostic logic signals and to output information relating to an overall operating state of the driver. The coding circuit includes a first portion to provide at its output first logic input signals indicating the last anomaly to occur since a system reset operation. The coding circuit also includes a second portion for coding the first logic input signals. The second portion includes a sequential logic network to receive the first logic input signals and at least one second logic signal indicating the current operating phase of the driver. The second portion provides, as a function of the first and second logic signals, a stable internal state to determine the output information in the form of an N bit coded word.

Abstract: A direct-comparison reading circuit for a nonvolatile memory array having a plurality of memory cells arranged in rows and columns, and at least one bit line, includes at least one array line, selectively connectable to the bit line, and a reference line; a precharging circuit for precharging the array line and reference line at a preset precharging potential; at least one comparator having a first terminal connected to the array line, and a second terminal connected to the reference line; and an equalization circuit for equalizing the potentials of the array line and reference line in the precharging step. In addition, the reading circuit includes an equalization line distinct from the reference line; and controlled switches for connecting, in the precharging step, the equalization line to the array line and to the reference line, and for disconnecting the equalization line from the array line and from the reference line at the end of the precharging step.

Abstract: The present invention relates to the positioning of the read/write transducer heads of an hard disk (HD) in a designated landing zone when requested or when the electrical power is removed from the drive. In particularly it relates to the detection of the back electromotive force (BEMF) of the motor involved in the positioning of the read/write transducer heads.

Abstract: A method of forming a doped region in an integrated circuit which includes a matrix of memory cells and lightly-doped drain transistors and which is fabricated by means of a process providing for a Self-Aligned Source masked etch and implant and for a selective salicidation of some doped regions, the doped region suitable for forming an integrated resistor and/or an abrupt-profile source/drain region of a transistor. The doped region is formed by introducing into a semiconductor layer of a first conductivity type a dopant of a second conductivity type and exploiting the SAS masked implant used to form source regions of the matrix of memory cells. At least a portion of a surface of the doped region is prevented from being salicidated by using as a protective mask a portion of a dielectric layer from which insulating sidewall spacers for the LDD transistors are formed.

Abstract: It is described a circuit generating a stable reference voltage with respect to temperature, which circuit is connected between first and second voltage references and comprises at least one current generating circuit adapted to inject a reference current into a resistive element connected between a base terminal of a bipolar transistor and an additional voltage reference. The bipolar transistor is connected between the first and second voltage references and to an output terminal of the generator circuit whereat the stable reference voltage with respect to temperature is. The generator circuit further comprises at least another resistive element, feedback connected between the output terminal of the generator circuit and the base terminal of the bipolar transistor to enable injecting additional current, having reverse dependence on temperature from the reference current, into the resistive element.

Abstract: A sensing device having a microelectromechanical structure made of semiconductor material, and a control loop for controlling the microelectromechanical structure, the microelectromechanical structure including a stator element and a rotor element electrostatically coupled together, and the control loop including a position interface supplying a position signal indicative of the position of the rotor element, and a one-bit quantizer receiving the position signal and supplying a corresponding bit sequence. The sensing device further includes a calibration device for calibrating the microelectromechanical structure, including a microactuator made of semiconductor material and coupled to the rotor element, and a driving circuit for driving the microactuator, and receiving the bit sequence and supplying to the microactuator a driving signal correlated to a mean value of the bit sequence in a given time window.

Abstract: A method of fabricating non-volatile memory devices integrated in a semiconductor substrate is presented. The memory devices include a matrix of non-volatile memory cells, each having floating-gate MOS transistors with associated gate electrodes, as well as control circuitry formed of MOS transistors also having gate electrodes. The method includes forming gate electrodes above the substrate, then depositing a first dielectric layer onto the entire exposed surface. Next the first dielectric layer is etched back to form isolating spacers on the side walls of the gate electrodes of the matrix cells. Then a second dielectric layer is deposited onto the entire exposed surface, and the memory matrix is overlaid with a protective layer. In the circuitry area, the second dielectric layer is etched back to form isolating spacers on the side walls of the gate electrodes of the circuitry transistors, while the floating-gate MOS transistors are protected.

Abstract: The protection circuit includes a reference voltage source and at least one circuit which are connected together via a switch. A memory element is connected to the input of the circuit, downstream of the switch. The switch is temporarily opened by a control signal generated by a monostable circuit when detecting switching of power elements belonging to an electronic device embedding the protection circuit. When the switch is open, the memory element supplies the circuit with the reference voltage previously stored. In this way, switching of the power element that might cause noise on the reference voltage cannot disturb the circuit and thereby cannot cause a faulty operation of the latter.