Abstract: A method is provided for carrying out a trimming operation on an integrated circuit having a trimming circuit portion which includes memory elements and a modification circuit for modifying the state of the memory elements, at least a first input or supply pin, an output pin, and a second supply pin. According to the method, a single pin is enabled to receive trimming data by biasing the pin to outside its operating range. A clock signal is obtained from a division of the bias potential of the pin, and the logic value of the trimming data is obtained from a different division of the bias potential of the pin. Serial acquisition of the data is enabled in accordance with the clock signal, and the data is transferred to the modification circuit.

Abstract: A voltage regulator for memory circuits has a differential stage having a non-inverting input terminal receiving a control voltage independent of the temperature; an inverting input terminal connected to a ground voltage reference; a feed terminal connected to a booster circuit adapted for producing a boosted voltage; and an output terminal connected to an output terminal of the voltage regulator, for producing an output voltage reference starting from the comparison of input voltages. The voltage regulator further comprises a connecting transistor inserted between the feed terminal and the output terminal of the differential stage, the connecting transistor being source follower having a control terminal connected to the output terminal of the differential stage, as well as a source terminal connected to the output terminal of the voltage regulator, in such a way as to self-limit the transition of the voltage on the output terminal.

Abstract: An electronic memory device organized into sections which are in turn divided into blocks formed of cells and their associated decoding and addressing circuits, the cells being connected in a predetermined circuit configuration and each block being included between two opposite contact regions which are interconnected by parallel continuous conduction lines referred to as the bit lines. In the present invention, at least one interruption is provided in each bit line near a contact region by inserting a controlled switch which functions as a block selector. Advantageously, the proposed solution allows each block to be isolated individually by enabling or disabling as appropriate the switches of the cascade connected blocks.

Abstract: A method of protecting data in a semiconductor electronic memory, which includes using a protected memory portion within the matrix and respective dedicated decoding portions for storing, into the protected portion, a protection code without the address area of the matrix. The protection code can only be written and/or read through a command interpreter.

Abstract: An electronic level shifter device having very low power consumption includes a first voltage reference from a power supply and a second voltage reference from a ground. The shifter device includes a circuit portion with a differential cell having an output terminal and at least a first and a second input terminal. On the output terminal is a level translated signal with respect to a signal present on one of said input terminals. The device further comprises an additional circuit portion connected to a node of the differential cell and comprising at least a pull-down component inserted between said node and the second voltage reference. The pull-down component can be a MOS transistor having its conduction terminals connected between said node and the second voltage reference and its gate terminal connected to the first voltage reference of power supply by means of a series of transistors.

Abstract: In a CMOS process for making dual gate transistors with silicide, high-voltage transistors with drain extensions are produced by first defining on a semiconductor substrate, active areas for low-voltage and high-voltage transistors. A gate oxide layer and a layer of polysilicon is deposited over the substrate, which is masked and etched to produce gates for the transistors. A dielectric layer is deposited to produce spacers to the sides of the transistor gate regions, then a mask partially shields the dielectric layer over the junctions of the high-voltage transistors while the spacers are being formed. Finally, the substrate is doped in the gate and active areas of the high-voltage transistor, and in the gate and active areas of the low-voltage transistor, except those areas that are blocked by the spacers.

Abstract: The method comprises forming an implantation screening layer of predetermined thickness on the wafer, forming, in the screening layer, a first rectilinear, elongate opening having a first width, and at least a second rectilinear, elongate opening substantially parallel to the first opening and having a second width smaller than the first width is formed on the screening layer. The wafer is then subjected to ion implantation with two ion beams directed in directions substantially perpendicular to the longitudinal axes of the openings and inclined to the surface of the wafer at predetermined angles so as to strike the openings from two opposite sides. The thickness of the screening layer, the widths of the openings, and the angles of inclination of the ion beams being selected in a manner such that the beams strike the base of the first opening for substantially uniform doping of the underlying area of the wafer, but do not strike the base of the second opening.

Abstract: Active areas and body regions are formed in a substrate for forming low voltage MOS transistors, high voltage MOS transistors, and EPROM cells. A thermal oxide layer is formed on the substrate, and a first polycrystalline silicon layer is formed on the thermal oxide layer. The polycrystalline silicon layer is selectively removed to form the floating gate electrodes of the EPROM cells, and the source and drain regions of the EPROM cells are also formed. The active areas for the high voltage MOS transistors are exposed, and a layer of high temperature oxide is formed and nitrided. The active area for the low voltage MOS transistors are exposed, and a layer of thermal oxide is formed on the exposed areas. A second polycrystalline silicon layer is deposited, which is then selectively removed to form the gate electrodes of the low voltage and high voltage MOS transistors, and the control gate electrodes of the EPROM cells.

Abstract: A method for erasing non volatile memories, in particular flash cells, that includes applying erasing pulses to the cells to be erased and to verify, after each pulse, the value of the threshold voltage of the cells. The erasing pulses are provided to the cells as long as the respective values of the threshold voltage are greater than the new values of threshold voltage corresponding to new data to be rewritten in the cells to be erased.

Abstract: A nonvolatile memory device has a signature code generator generating a present signature code from an algorithm modified dynamically as a function of predefined varying parameters. A variable parameter may be the address of a memory cell being addressed; in this case the output of the code generator is a function of data read from the cell array, the previously calculated signature code and the address of the read data. The data are read in sequence, using an internal clock generated by an internal clock oscillator. In test mode, the memory is scanned sequentially, beginning from any memory location, selected randomly, and the signature code varies in dynamic way; at the end of memory scanning, the signature code is compared to an expected result.

Abstract: A process for forming floating gate non-volatile memory cells in a cell matrix with associated control circuitry comprising both N-channel and P-channel MOS transistors is provided. The process includes forming active areas in a substrate for the cell matrix and the associated control circuitry. A first thin oxide layer and a first polysilicon layer are deposited on the active areas to produce floating gate regions of the memory cells, and a second dielectric layer is deposited on the active areas. A second polysilicon layer is then deposited on the active areas. A masking and etching step is performed for exposing the substrate for the associated control circuitry followed by the deposition of a third polysilicon layer. The third polysilicon layer is defined to produce the gate regions of the transistors for the associated control circuitry while the third polysilicon layer is removed from the cell matrix.

Abstract: An amplifier stage having a first and a second transistor connected in series to each other between a first and a second reference potential line. The first transistor has a control terminal connected to an input of the amplifier stage through a first inductor, a first terminal connected to the second reference potential line through a second inductor, and a third terminal connected to a first terminal of the second transistor. The second transistor has a second terminal forming an output of the amplifier stage, and connected to the first reference potential line through a load resistor. To improve the noise figure, a matching capacitor is connected between the control terminal and the first terminal of the first transistor.

Abstract: A manufacturing process providing a zener diode formed in an N-type well housing a first N-type conductive region and having a doping level higher than the well, and a second P-type conductive region arranged contiguous to the first conductive region. The first conductive region is connected, through a third N-type conductive region having the same doping level as the first conductive region, to a conductive material layer overlying the gate oxide layer to be protected. The third conductive region, the well, and the substrate form an N+/N/P diode that protects the gate oxide layer during manufacture of the integrated device from the deposition of the polycrystalline silicon layer that forms the gate regions of the MOS elements.

Abstract: A method including: forming doped regions on a monocrystalline substrate; growing an epitaxial layer; forming trenches in the epitaxial layer extending to the doped regions; anodizing the doped regions in an electro-galvanic cell to form porous silicon regions; oxidizing the porous silicon regions; removing the oxidized porous silicon regions to form a buried air gap; thermally oxidizing the substrate to grow an oxide region from the walls of the buried air gap and the trenches, until the buried air gap and the trenches themselves are filled.

Abstract: A memory counter circuit includes a plurality of mutually connected counter stages, an internal address bus interfaced with each one of the counter stages for sending an external address signal to each one of the counter stages, a circuit for loading the external address signal onto the internal address bus, and an enabling circuit for enabling a connection between the internal bus and each one of the counter stages. The enabling circuit may be driven by a true address latch enable signal. The memory counter circuit may further include a circuit for generating the true address latch enable signal starting from an external address latch signal and a fast address latch enable signal for driving the circuit for loading the external address signal onto the internal address bus. A signal generation circuit may also be included for generating clock signals for synchronizing each one of the counter stages. The synchronization signals are preferably not simultaneously active.

Abstract: A method of forming source and drain regions for LV transistors that includes the steps of forming sacrificial spacers laterally to LV gate regions; forming LV source and drain regions in a self-aligned manner with the sacrificial spacers; removing the sacrificial spacers; forming HV gate regions of HV transistors; forming gate regions of selection transistors; forming control gate regions of memory transistors; simultaneously forming LDD regions self-aligned with the LV gate regions, HV source and drain regions self-aligned with the HV gate regions, source and drain regions self-aligned with the selection gate region and floating gate region; depositing a dielectric layer; covering the HV and memory areas with a protection silicide mask; anisotropically etching the dielectric layer, to form permanent spacers laterally to the LV gate regions; removing the protection silicide mask; and forming silicide regions on the LV source and drain regions and on the LV gate regions.

Abstract: A method is for self-test and correction of errors due to a loss charge for a flash memory including an array or matrix of cells (bits), organized in rows and columns, erasable and programmable by whole sectors in which the matrix is divided.

Abstract: A PET decoder for an ATM network has a modular architecture including a processing unit having various memories and a processing pipeline for constructing from a block of m data of a certain number of bits, a square matrix A based on a vector D of relative points over the Galois field. The processing pipeline also decomposes by triangular factorization the square matrix A and solves the subsystem of equations by simple substitution. The decoder also includes a control unit interfacing with the ATM network, a programmable parallel processor, a random access memory and the processing unit.

Abstract: A pulse generator circuit for non-volatile memories, is disclosed, including a circuit for determining the instant at which a pulse for incrementing a counter of the memory is generated and generating an increment pulse duration start signal; a circuit for determining the minimum amplitude of the increment pulse and generating an increment pulse duration end signal; a first logic circuit for enabling the generation of the increment pulse based upon the increment pulse duration start and end signals; and an increment pulse generation circuit for generating or suppressing the increment pulse of the counter of the memory, based upon the current condition of the memory.

Abstract: An integrated electronic device having a first charge pump, intended to drive a first line having a high capacitive load, and a second charge pump having a high current pumping capacity and intended to drive a second line, a controlled switch is interposed between the outputs of the two pumps, such as to connect the output of the high current capacity pump to the first line, to charge the first line quickly to the preset voltage, without the first charge pump being oversized. When the voltage present on the first line becomes greater than the voltage at the output of the second charge pump, owing to the current required by the second line, the switch is opened. A common phase generator which drives both the pumps is also provided.