Abstract: Silver interconnects are formed by etching deep grooves into an insulating layer over the contact regions, exposing portions of the contact regions and defining the interconnects. The grooves are etched with a truncated V- or U-shape, wider at the top than at any other vertical location, and have a minimum width of 0.25 &mgr;m or less. An optional adhesion layer and a barrier layer are sputtered onto surfaces of the groove, including the sidewalls, followed by sputter deposition of a seed layer. Where aluminum is employed as the seed layer, a zincating process may then be optionally employed to promote adhesion of silver to the seed layer. The groove is then filled with silver by plating in a silver solution, or with silver and copper by plating in a copper solution followed by plating in a silver solution.

Abstract: Presented is a process for manufacturing circuit structures of the SOI type integrated on a semiconductor substrate having a first type of conductivity. The process includes forming at least one well with a second type of conductivity in the semiconductor substrate and forming a hole within the well. The hole is then coated with an insulating coating layer, and an opening is formed through the insulating coating layer at the bottom of the hole. The hole is then filled with an epitaxial layer grown from a seed that was made accessible through the opening in the hole.

Abstract: The memory cell is of the type with a single level of polysilicon, and is produced in a substrate of semiconductor material with a first type of conductivity, and comprises a control gate region with a second type of conductivity, formed in the substrate in a first active region; regions of source and drain with the second type of conductivity, formed in the substrate in a second active region; and a floating gate region which extends transversely relative to the first and the second active regions. The control gate region is surrounded by a first well with the first type of conductivity, which in turn is surrounded, below and laterally, by a third well with the second type of conductivity. The regions of source and drain are accommodated in a second well with the first type of conductivity, which in turn is surrounded below and laterally by a fourth well with the second type of conductivity.

Abstract: A method of manufacturing an integrated circuit is provided. According to the method, first and second stop layers are deposited on a first dielectric layer that covers a first metallization level. The second stop layer is selectively etched with respect to the first stop layer, and the first stop layer is selectively etched with respect to the first dielectric layer. A second dielectric layer and a third stop layer are deposited. The third stop layer is selectively etched with respect to the second dielectric layer, and the first and second dielectric layers are selectively etched with respect to the stop layers so as to form trenches in the second dielectric layer and holes in the first dielectric layer. Additionally, an integrated circuit is provided that includes first and second metallization levels. A dielectric layer is located between the metallization levels, and a first stop layer is located between the dielectric layer and the second metallization level.

Abstract: A circuit to detect and record the occurrence of a surge in the supply voltage applied to an integrated circuit includes a detection circuit for providing a control signal if a voltage surge is detected. The circuit also includes a high voltage circuit, which produces a high programming voltage from the supply voltage if a voltage surge is detected, and a memory cell. The detection circuit may include a capacitor divider bridge, a voltage source, and a comparator. The circuit is particularly advantageous for use with electrically programmable memories.

Abstract: A process for forming an electrical resistance in an integrated MOS transistor includes applying a first voltage to the source and gate of the MOS transistor, and applying a second voltage to the drain of the MOS transistor. A prebiasing voltage is applied to the substrate of the MOS transistor to make the base/emitter junction of a parasitic bipolar transistor of the MOS transistor conduct. The first and second voltages are capable of initiating a breakdown of the MOS transistor by an avalanche of the drain/substrate junction, an irreversible breakdown of the drain/substrate junction, and a short circuit between the drain and the source.

Abstract: A switched operational amplifier with fully differential topology, alternately switchable on and off, and a control circuit. The operational amplifier has a first differential output (4a) and a second differential output, and a control terminal. The control circuit includes a capacitive detecting network including a first capacitor and a second capacitor connected between the first and second differential outputs and a common-mode node, and a third capacitor connected between the common-mode node and ground in a first operative condition, and between the common-mode node and the supply voltage in a second operative condition. A control transistor is connected between the common-mode node and the control terminal of the operational amplifier and supplies a control current correlated to the voltage on the common-mode node. A switchable voltage source, connected to the common-mode node, supplies a desired voltage in a first operative condition, when the operational amplifier is off.

Abstract: A method and circuit are disclosed for controlling the current level of a differential logic circuit having a current source, input transistors which perform current steering based upon the input to the differential logic circuit, and load transistors. The circuit includes a first transistor that forms a current mirror with the current source, a second transistor coupled to the load transistors so that the operating characteristics of the load transistors substantially match the operating characteristics of the second transistor, and current source circuitry coupled between the first and second transistors. The current level selected in the current source circuitry sets the current level in the differential logic circuit and the resistance of the load transistors so that the output voltage swing of the differential logic circuit stays within an acceptable range of voltages, regardless of the selected current level.

Abstract: A computer system having a memory system where at least some of the memory is designated as shared memory. A transaction-based bus mechanism couples to the memory system and includes a cache coherency transaction defined within its transaction set. A processor having a cache memory is coupled to the memory system through the transaction based bus mechanism. A system component coupled to the bus mechanism includes logic for specifying cache coherency policy. Logic within the system component initiates a cache transaction according to the specified cache policy on the bus mechanism. Logic within the processor responds to the initiated cache transaction by executing a cache operation specified by the cache transaction.

Abstract: An SC filter with intrinsic anti-alias function for adjustably decreasing or increasing the amplitude of audio signals in a predetermined frequency range. The SC filter includes a filter module having an RC network with at least one frequency-response-determining RC member whose resistor component R is realized in SC technology. The SC filter also includes a setting means connected to the filter module such that its setting determines the frequency response of the SC filter. The setting means also renders possible a neutral setting in which the effective audio signal path of the SC filter circumvents the filter module so that no decrease or increase of the amplitude of individual frequency portions takes place. An anti-alias low pass filter unit is connected into the audio signal path when the setting means is not set to the neutral setting and the anti-alias low pass filter unit is not located in the audio signal path when the setting means is set to the neutral setting.

Abstract: The control device includes an output amplifier stage ETS supplied by a main supply for controlling the vertical scan of the spot, and an auxiliary supply capable of delivering an overvoltage and a first two-way switch connected to the output stage and controllable to allow the overvoltage to be delivered to the vertical deflection circuit for flyback of the spot. The output stage is a stage having at least two transistors which are capable of operating in alternating switching mode, at least for control of the vertical scan of the spot, this stage being associated with a smoothing filter connected to the common terminal of the two transistors. The device includes a second two-way switch connected between a first transistor of the output stage and a first terminal of the main supply and controllable to prevent delivery of the overvoltage during control of the vertical scan of the spot.

Abstract: An electronic circuit is for optimizing or reducing switching losses in current-driven power devices and includes a switching power device connected to an electric load. The power devices has at least one control terminal arranged to receive a predetermined drive current value produced by a first current generator. The control terminal also receives an additional drive current portion produced by a second independent current generator. Advantageously, the electronic circuit includes a control circuit for controlling a switch connected between the second current generator and the control terminal of the switching power device during the turn-on and turn-off phases of the power device.

Abstract: A bipolar transistor is produced by processes employed in the manufacture of CMOS nonvolatile memory devices, and is part of an integrated circuit. The integrated circuit includes a semiconductor substrate having a first type of conductivity, a PMOS transistor formed in said substrate, an NMOS transistor formed in said substrate, and the bipolar transistor.

Abstract: A process for manufacturing a ferroelectric capacitor includes the steps of forming a first plate of a noble metal, preferably platinum, above an insulating layer of a wafer; forming a dielectric material layer with ferroelectric properties; and forming a second plate of a noble metal above said dielectric material layer. The first plate and the second plate are formed by electrochemical deposition of a metal.

Abstract: There is provided a digital data transmission system that includes a first unit transmitting a first MLT3 signal, a second unit receiving the first MLT3 signal, and transformers. The second unit includes an equalizer receiving the first MLT3 signal and outputting a second MLT3 signal that is input to a recovery module for the transmitted digital data, and a device placed in feedback to the equalizer. The device receives the second MLT3 signal and outputs a third low frequency signal that is added to the first MLT3 signal. The device has a translation block for the up or down or no translation of the second MLT3 signal according to the low or high or intermediate value of such signal, and a low pass filter receiving the signal output from the translation block and outputting the third signal containing the low frequency component of the second MLT3 signal.

Abstract: Processes are provided for fabricating a substrate having a silicon-on-insulator (SOI) or silicon-on-nothing (SON) architecture, which are applicable to the manufacture of semiconductor devices, especially transistors such as those of the MOS, CMOS, BICMOS, and HCMOS types. In the fabrication processes, a multilayer stack is grown on a substrate by non-selective full-wafer epitaxy. The multilayer stack includes a silicon layer on a Ge or SiGe layer. Active regions are defined and masked, and insulating pads are formed so as to be located around the perimeter of each of the active regions at predetermined intervals and placed against the sidewalls of the active regions. The insulating trenches are etched, and the SiGe or Ge layer is laterally etched so as to form an empty tunnel under the silicon layer. The trenches are filled with a dielectric. In the case of an SOI archiutecture, the tunnel is filled with a dielectric.

Abstract: The low temperature-corrected constant voltage generator device includes a reference voltage generator, an amplifier connected between the reference voltage generator and an output terminal and a voltage divider connected to an input of the amplifier in order to supply a feedback voltage to the amplifier. The divider includes at least one first resistor in series with an element having, at least in the low temperature range, an impedance with a temperature dependence behavior different from that of the first resistor, to supply a lower feedback in the low temperature range.

Abstract: An operational amplifier includes an input transconductor stage with differential inputs and an output, an output stage, and at least one intermediate stage connected between the input stage and the output stage so as to form an amplifier chain. The intermediate stage includes a common-emitter bipolar transistor between first and second power supply terminals, and at least one feedback resistor connected between the bipolar transistor emitter and one of the power supply terminals. The intermediate stage also includes at least one feedback capacitance connected between the emitter terminal of the transistor and an output of a next stage.

Abstract: A method of and system for providing user input to a computer, or the like, having a display by detecting a change in fingerprint pattern of a user. The system controls the position of a pointer on a display by detecting motion of ridges and pores of a fingerprint of a user and moving the pointer on the display according to detected motion of the ridges and pores of the fingerprint. The system captures successive images of the fingerprint ridges and pores and detects motion of the ridges and pores based upon the captured successive images.

Abstract: A contact structure provides electrical contact between two polycrystalline silicon interconnect layers. The lower layer has a silicide layer on its upper surface. The upper polycrystalline silicon layer can be doped with a different conductivity type, and makes an ohmic contact with the silicided region of the lower polycrystalline silicon layer.