Abstract: An electronic device for computing a Fourier transform having a pipeline architecture includes at least one processing stage with a radix equal to 4. Each processing stage includes elementary processing for performing process operations for Fourier transforms of size equal to 4 on data blocks. Each processing stage also includes an elementary storage that includes a random access memory. In particular, the random access memory is a single-access memory with a storage capacity equal to 3N/4 data bits. The size of the data block processed by this stage is equal to N.

Abstract: A circuit for providing a reference voltage, including a first transistor of bipolar type, the emitter of which provides the reference voltage and the collector of which is connected to a first supply pole, a second MOS-type transistor, the drain of which is connected to the base of the first transistor and the source of which is connected to a second supply pole, a control block, an output of which is connected to the gate of the second transistor and an input of which is connected to the emitter of the first transistor, a capacitor connected to the output of the control block and coupled to the first supply pole via a first impedance, and a second impedance connected on the one hand to the second transistor and on the other hand to the connection point between the capacitor and the first impedance.

Abstract: A circuit extends the output voltage range of an integrator circuit wherein the input signal is used to produce an output signal, and the voltage of the output signal develops monotonically within a predetermined range of possible values. The integrator circuit is driven within an integration time period such that each time the signal at its output reaches a limit of the range of values, the integrator circuit starts a subsequent integration stage of the input signal in which the output signal develops again within the above-mentioned range. This takes place by resetting the integrator circuit or by a reversal of the characteristic slope of the output signal. This is combined with storing the number of occasions on which these interventions have occurred as determined by a scounter.

Abstract: A method for forming by molding a plastic protective package for an electronic integrated circuit that includes an electronic device activated from the outside of said protective package. The method includes: dispensing a covering layer of elastic material on a portion of said electronic device; shaping said covering layer to form a projecting portion from a surface of said electronic device; molding said electronic integrated circuit in said plastic protective package using a mold including at least a half-mold abutting against said projecting portion; and obtaining a hole or a window formed in alignment with said projecting portion in said protective package.

Abstract: On a semiconductor material body housing an electronic device a peripheral region of semiconductor material and at least one pad are initially formed. The peripheral region is connected to a first terminal of the electronic device and extends on at least one peripheral portion of the semiconductor material body. The pad is insulated from the semiconductor material body and is electrically connected to a second terminal of the electronic device. The semiconductor material body is fixed to a support body formed by a blank belonging to a reel. The pad is connected by a wire to an electrode formed by the blank. Next, a connection region is formed on the peripheral region and surrounds, at least partially, the semiconductor material body and the support body. The connection region is advantageously obtained by galvanic growth.

Abstract: A managing system manages a plurality of VRMs associated with a plurality of microprocessors and connected in parallel together between first and second voltage references, the VRMs having output terminals connected together and arranged to communicate over a common bus. The managing system includes an error amplifier being input an output voltage signal from the VRM plurality, a reference voltage, and a droop voltage produced through an equivalent droop resistor receiving an output current signal from the VRM plurality and being connected to the common bus. The error amplifier effects a comparison of the input signals to generate a control voltage signal to the VRM plurality. Advantageously, the managing system comprises a controller connected to the equivalent droop resistor.

Abstract: A high-efficiency electronic circuit generates and regulates a supply voltage and includes a charge-pump voltage multiplier which is associated with an oscillator and has an output connected to a voltage regulator in order to ultimately output said supply voltage. Advantageously, the circuit comprises a first hysteresis comparator having as inputs the regulator output and the multiplier output, and comprises a second hysteresis comparator having as inputs a reference potential and a partition of the voltage presented on the regulator output. The comparators are structurally and functionally independent of each other, and their outputs are coupled to the oscillator through a logic circuit to modulate the oscillator operation.

Abstract: A contact structure for a ferroelectric memory device 13 integrated in a semiconductor substrate and includes an appropriate control circuitry and a matrix array of ferroelectric memory cells, wherein each cell includes a MOS device connected to a ferroelectric capacitor. The MOS device has first and second conduction terminals and is covered with an insulating layer. The ferroelectric capacitor has a lower plate formed on the insulating layer above the first conduction terminals and connected electrically to the latter, which lower plate is covered with a layer of a ferroelectric material and coupled capacitively to an upper plate. Advantageously, the contact structure comprises at least a plurality of plugs filled with a nonconductive material between the first conduction terminals and the ferroelectric capacitor, and comprises a plurality of plugs filled with a conductive material for the second conduction terminals or the control circuitry.

Abstract: This invention relates to a method for manufacturing a semiconductor device having polysilicon lines with micro-roughness on the surface. The micro-rough surface of the polysilicon lines help produce smaller grain size silicide film during the formation phase to reduce the sheet resistance. The micro-rough surface of the polysilicon lines also increases the effective surface area of the silicide contacting polysilicon lines thereby reduces the overall resistance of the final gate structure after metallization.

Abstract: A rectifying integrator of an input signal with full output dynamics, relative to a voltage reference intermediate with respect to the dynamics of the input signal, includes a first line of integration having at least one integrator for integrating that portion of the input signal that exceeds the voltage reference, and includes a hold capacitor coupled in cascade to the integrator. The rectifying integrator includes a second line of integration, identical to the first line of integration, for integrating that portion of the input signal that remains below the voltage reference. An adder output stage generates an output signal equal to the difference between the voltages existing on the hold capacitors of the first and second lines of integration.

Abstract: A buffer circuit includes an input for receiving a logic signal, and a transfer circuit for transferring the logic signal from the input to an output of the buffer circuit. The transfer circuit includes at least one logic gate having a trip point sensitive to a supply voltage of the buffer circuit. The buffer circuit further includes a delivery circuit for delivering an inhibit signal having a predetermined duration when the logic signal has a trailing edge and/or leading edge, and an inhibit circuit for inhibiting the transfer circuit and for isolating the output of the buffer circuit from the input of the buffer circuit when the inhibit signal is delivered. A storage circuit holds a logic value of the logic signal at the output of the buffer circuit when the inhibit signal is delivered.

Abstract: A microactuator comprises a stator element and a rotor element which are capacitively coupled. The rotor element comprises a suspended mass and a plurality of movable drive arms extending radially from the suspended mass and biased at a reference potential. The stator element comprises a plurality of first and second fixed drive arms associated with respective movable drive arms and biased at a first drive potential. A mechanical damping structure is formed by at least one movable damping arm extending radially from the suspended mass and by at least one first and one second fixed damping arm associated with the movable damping arm and biased at said reference potential, to dampen settling oscillations of the rotor element.

Abstract: A decoding method for a Huffman code includes receiving a continuous stream of coded data each including a variable number of bits at least equal to a minimum number, and obtaining from each item of coded data a corresponding item of source data. The method includes providing a decoding memory structure comprising, for each value of an initial group of bits including a number not greater than the minimum number and for each value of each further bit, a record formed by a flag having an end-of-decoding value or a not end-of-decoding value and a field indicating the source data or the records associated with the values of an immediately following bit depending on whether the flag has, respectively, the end value or the not end value. The record corresponding to the value of the initial group is accessed.

Abstract: A complementary logic circuit is provided which provides improved switching times over known complementary logic circuits. The circuit includes a further n-type transistor connected in series between a p-type and an n-type transistor. This additional n-type transistor has its gate permanently connected to an upper supply voltage, Vdd. When switching occurs the n-type transistor is effectively open circuit. This allows the first n-type transistor to switch on by a substantial amount quite quickly without ‘fighting’ the presently conducting p-type transistor. When the first n-type transistor has been turned substantially on second transistor becomes conductive. Then the p-type transistor is substantially turned off and no longer opposes the turning on of the first n-type transistor.

Abstract: A circuit and method for reading a multiple-level floating-gate memory is provided. The reading is done by a gate bias voltage VP that is equal to the voltage needed to obtain a predetermined reference current Iref in the selected storage transistor. The decoding of the stored data element is done by the decoding of the bias voltage VP. Thus the circuit and method reduces the current flowing through the transistors during the reading and reduces the mean electrical stress undergone during each read operation.

Abstract: A ratio logic gate has a current mirror controlled by the pull-down transistors and supplying a half size pull-down transistor. When one or more of the input pull-down transistors is on, the mirror current overcomes the output pull-down transistor to provide a high potential output. Process tolerances between p and n type devices is thus avoided.

Abstract: A charge pump voltage booster circuit for generating, from a first voltage supplied at the input to the circuit, an output voltage with an absolute value that is higher than the first voltage, comprises at least one stage having a charge pass element and a charge storage capacitor with a first plate connected to an output of the charge pass element and a second plate controlled by a square-wave control signal of period varying between a reference voltage and the first voltage, supplied to the second plate of the capacitor by means of a driver circuit comprising a pull-up transistor and a pull-down transistor connected in series between the first voltage and the reference voltage. Means of overdriving at least one of the said transistors, either the pull-up transistor or the pull-down transistor, supply to the said at least one transistor a firing control voltage that has a higher absolute value than the first voltage.

Abstract: A process for manufacturing a resistive structure that has a polysilicon strip laid above a semiconductor substrate is presented. The process begins by using a mask to cover the polysilicon strip. Then, several apertures are made in the mask until portions of the semiconductor strip are uncovered. Next, a dopant is implanted in the polysilicon semiconductor strip through the apertures. Finally, the resistive structure is subjected to a thermal process for diffusing the dopant in such a way to obtain a variable concentration profile in the semiconductor strip.

Abstract: A field-effect transistor and a method for its fabrication are described. The transistor includes a monocrystalline channel region extending from a monocrystalline body region of a semiconductor substrate. First and second source/drain regions laterally adjoin opposite sides of the channel region and are electrically isolated from the body region by an underlying first dielectric layer. The source/drain regions include both polycrystalline and monocrystalline semiconductor regions. A conductive gate electrode is formed over a second dielectric layer overlying the channel region. The transistor is formed by selectively oxidizing portions of a monocrystalline semiconductor substrate and then removing portions of the oxidized substrate. The resulting structure includes a body region of the substrate having overlying first and second oxide regions, with a protruding channel region extending from the body region between the oxide regions.

Abstract: A MOS technology power device is described which comprises a plurality of elementary active units and a part of said power device which is placed between zones where the elementary active units are formed. The part of the power device comprises at least two heavily doped body regions of a first conductivity type which are formed in a semiconductor layer of a second conductivity type, a first lightly doped semiconductor region of the first conductivity type which is placed laterally between the two body regions. The first semiconductor region is placed under a succession of a thick silicon oxide layer, a polysilicon layer and a metal layer.