Abstract: A process for color adjustment of a color monitor including a cathode-ray tube and a brightness adjustment module includes providing a nominal brightness signal downstream of a white level adjustment module for adjusting a white level and upstream of a black level adjustment module for adjusting a black level. The process also includes setting a voltage required to obtain a black color image, setting a voltage required to obtain a white color image, providing the nominal brightness signal upstream of the white level adjustment module, and setting the voltage required to obtain the black color image.

Abstract: A device is provided for calculating mutual phase shift of first and second incident signals. The device includes a first pair of blocks associated with the first incident signal, a second pair of blocks associated with the second incident signal, checking circuit, and post-processing circuit. Each of the blocks has storage elements for storing a predetermined set of samples of the corresponding incident signal. In the presence of minimum samples or maximum samples of both incident signals, the checking circuit stores a first set of samples relating to the first incident signal in one of the blocks of the first pair and a first set of samples relating to the second incident signal in the counterpart block of the second pair, and then stores the following sets of samples of each incident signal alternately in the two blocks of each pair. The checking circuit delivers a block validation signal when a set of samples has been completely stored in the storage elements of one of the blocks.

Abstract: An angular speed sensor comprises a pair of mobile masses which are formed in an epitaxial layer and are anchored to one another and to the remainder of the device by anchorage elements. The mobile masses are symmetrical with one another, and have first mobile excitation electrodes which are intercalated with respective first fixed excitation electrodes and second mobile detection electrodes which are intercalated with second fixed detection electrodes. The first mobile and fixed excitation electrodes extend in a first direction and the second mobile and fixed detection electrodes extend in a second direction which is perpendicular to the first direction and is disposed on a single plane parallel to the surface of the device.

Abstract: A voltage regulator includes a regulation MOS transistor with low serial resistance having a first terminal connected to a voltage source and a second terminal connected to the output of the voltage regulator and an amplifier having an output driving a gate of the transistor. The gate is driven based upon a difference between a reference voltage and a feedback voltage. The regulator may also include an anti-overshoot switch with a first terminal connected to the gate of the regulation MOS transistor and a second terminal is taken to a potential for turning the regulation MOS transistor off. A switch controller closes the switch when the output voltage of the regulator is higher than a first threshold. The first threshold may be higher than the nominal value of the output voltage.

Abstract: An integrated circuit voltage ramp generator is presented. The circuit includes at least one operational amplifier having a non-inverting input terminal connected to a voltage reference, and having an output terminal coupled in a feedback relationship to an output terminal of the generator circuit. The ramp voltage generator further includes a first storage capacitance connected between the non-inverting input terminal of the operational amplifier and a ground reference, which is loaded by means of a second pumping capacitance connected in parallel to the first capacitance. The pumping and voltage generation is and controlled by a series of passgates coupled to clock signals.

Abstract: The data management method applies to a multilevel nonvolatile memory device having a memory array formed by a plurality of memory cells. Each of the memory cells stores a number of bits that is not an integer power of two, for example three. In this way, one data byte is stored in a non-integer number of memory cells. The managing method includes storing, in a same clock cycle, a data word formed by a plurality of bytes, by programming a preset number of adjacent memory cells. Reading is performed by reading, in a same clock cycle, the stored data word.

Abstract: The multilevel memory device has a memory section containing cells that can be programmed with a predetermined number of levels greater than two, i.e., a multilevel array, and a memory section containing cells that can be programmed with two levels, i.e., a bilevel array. The multilevel array is used for storing high-density data, for which speed of reading is not essential, for example for storing the operation code of the system including the memory device. On the other hand, the bilevel array is used for storing data for which high speed and reliability of reading is essential, such as the BIOS of personal computers, and the data to be stored in a cache memory. The circuitry parts dedicated to programming, writing of test instructions, and all the functions necessary for the operation of the memory device, can be common to both arrays.

Abstract: A method to protect the contents of an electronic document through an encryption system based on an initial confusing step in a scrambler and a subsequent diffusion step in a chaotic processor, both steps being of a chaotic type. Initially, encryption keys and an initial chaotic value are acquired; input character strings are acquired; and diffused character strings are calculated using the input character strings, the encryption keys, and previous diffused character strings. After a certain number of iterations, sets of diffused character strings are added to subsequent chaotic values generated by a chaotic processor to obtain encrypted words. Decryption is obtained through two successive operations, wherein the encrypted words are added to chaotic values identical to the encryption values and subtracted from previously decrypted words using an unscrambler element having a structure similar to that of the scrambler and using identical encryption keys.

Abstract: A protection device includes a switching transistor (M11), connected between the gate of the output transistor (TS1) and ground, and a control circuit (CM), connected to the gate of the switching transistor (M11), which are capable of ensuring that the switching transistor (M11) is off when there is no electrostatic discharge at the drain of the output transistor (TS1) and capable of turning the switching transistor (M11) on when there is an electrostatic discharge at the drain of the output transistor (TS1).

Abstract: An integrated device comprises a first conductive region and a first insulating region of dielectric material covering the first conductive region. A first through region of electrically conductive material extends inside the first insulating region, and is in direct electrical contact with the first conductive region. A second conductive region, arranged above the first insulating region, is in a position not aligned and not in contact with the first through region. A second insulating region of dielectric material covers the second conductive region. A second through region of electrically conductive material extends inside the second insulating region as far as the first through region and is aligned and in direct electrical contact with the first through region. A third conductive region, arranged above the second insulating region, is aligned and in direct electrical contact with the second through region.

Abstract: An internal addressing structure for a semiconductor memory with at least two memory banks, includes a counter associated for operation with each memory bank and capable of generating sequences of digital codes for addressing locations in the corresponding bank, a first circuit for causing a selective updating of the counters, a second circuit for loading into the counters a common initial digital code, forming part of an initial address supplied to the memory from the outside through an addressing line bus, corresponding to an initial memory location, and a third circuit capable of detecting a first signal, supplied to the memory from the outside and indicating the presence of a digital code on the bus, to cause the common initial digital code to be loaded into the counters.

Abstract: An integrated circuit chip includes an RC oscillator circuit. The frequency of the output signal generated by the oscillator output signal is set as a function of a value of an included internal resistor integrated on the chip. An external resistor may be connected to the chip to allow a user to manipulate the oscillator output signal frequency. A detection circuit on the chip detects the presence of the connected external resistor. Responsive to that detection, a substitution circuit operates to substitute the connected external resistor for the internal resistor in the RC oscillator circuit. This effectuates a change of the frequency of the oscillator output signal to instead be set as a function of a value of that connected external resistor.

Abstract: An architecture handles internal voltages in a non-volatile memory array which is split into at least first and second mutually independent banks. The architecture includes first and second pluralities of generators for generating at least one of the internal voltages, which are separate from each other and connected to the first and second banks, respectively, of the nonvolatile memory array; and a control system connected to the pluralities of generators to handle the correct activation of the different generators in the different conditions of the memory array operation.

Abstract: A column register of an integrated circuit memory, notably in EEPROM technology, is utilized in a method of writing a data word of 2p bits in the memory, where p is a non-zero whole number. The method includes the following steps: 1) erasing all the cells of the word; 2) loading 2q data in 2q high-voltage latches (HV1, HV3, HV5, HV7), and loading 2p-2q other data in the 2p-2q low-voltage latches (LV0, LV2, LV4, LV6); and 3) programming 2q cells of the memory (M0, M2, M4, M6) as a function of the data memorized in the 2q high-voltage latches; as well as repeating 2p-q−1 times the following steps: 4) loading, in the 2q high-voltage latches, of 2q other data that were loaded in the 2q low-voltage latches at step 2); and 5) programming 2q other cells of the memory (M1, M3, M5, M7) as a function of the data memorized in the 2q high-voltage latches.

Abstract: A feedback control circuit is for the current in a load formed by a winding in series with a current sensing resistor, coupled to a full-bridge output stage, an amplifier coupled to the terminals of the sensing resistor, and a controller fed with the output of the amplifier and with a voltage reference and producing a correction signal. The circuit has a PWM converter for generating a pair of control signals. The PWM converter includes an up/down counter producing a count value and logic circuitry that produces the twos-complement of the correction signal. A pair of registers are coupled to the outputs of the controller and of the logic circuitry. A first comparator coupled to the outputs of the counter and of the first register produces the first control signal, if the count signal exceeds the value stored in the first register. A second comparator coupled to the counter and to the second register produces the second control signal, if the count signal overcomes the value stored in the second register.

Abstract: An integrated circuit for producing a small slope voltage ramp includes a circuit for generating a periodic triangular current signal, and a circuit for generating, at the beginning of each period of the triangular signal, a pulse of a certain duration which is much smaller than the period of the triangular signal. A control loop is input at a node with the triangular current signal and produces the desired slow voltage ramp on the output node. The control loop includes a first hold circuit coupled to the input node via a first switch controlled by the pulse, and a transconductance operational amplifier, whose inputs are respectively coupled to the input node and to the output node. Also, the control loop includes a second hold circuit coupled to the output of the operational transconductance amplifier via a second switch controlled in a complementary manner with respect to the first switch.

Abstract: This invention relates to a method for manufacturing a semiconductor device having polysilicon lines with micro-roughness on the surface. The micro-rough surface of the polysilicon lines help produce smaller grain size silicide graiicide film during the formation phase to reduce the sheet resistance. The micro-rough surface of the polysilicon lines also increases the effective surface area of the silicide contacting polysilicon lines thereby reduces the overall resistance of the final gate structure after metallization.

Abstract: The present invention refers to a current generator able to provide in alternative to a first terminal a first current and a second current in response to a control signal. Particularly it refers to a current generator usable for the adaptive biasing of modulators of the sigma-delta type. In an embodiment the current generator is able to provide in alternative to a first terminal (70) a first current and a second current in response to a control signal (CK), characterized by comprising: a first current generator (40) able to provide said first current; a second current generator (41) able to provide said second current; commutation means (46) able to connect in alternative to said first terminal (70) said first current and said second current in response to said control signal (CK).

Abstract: An optimized method of computing the value of the degree of membership of a fuzzy variable defined within a universe of discourse that is discreted into a finite number of points by way of a membership function thereof, wherein the membership function is quantified into a finite number of levels corresponding to a finite number of degrees of truth, and is stored as a characteristic value of each subset of fuzzy variable values being all mirrored in one value of said degree of membership corresponding to one of said levels. The computing method includes generating a binary sequence; generating an address signal from the bits in the binary sequence; reading the contents of the memory storing the membership functions at each address signal to obtain a characteristic value; and comparing the characteristic value with the value of a fuzzy input variable.

Abstract: A contact structure for semiconductor devices which are integrated on a semiconductor layer is provided. The structure comprises at least one MOS device and at least one capacitor element where the contact is provided at an opening formed in an insulating layer which overlies at least in part the semiconductor layer. Further, the opening has its surface edges, walls and bottom coated with a metal layer and filled with an insulating layer.