Abstract: A multilevel nonvolatile memory includes a supply line supplying a supply voltage, a voltage boosting circuit supplying a boosted voltage, higher than the supply voltage, a boosted line connected to the voltage boosting circuit and a reading circuit including at least one comparator. The comparator includes a first and a second input, a first and a second output, at least one amplification stage connected to the boosted line, and a boosted line latch stage connected to the supply line.

Abstract: A switching regulator circuit produces a varying reference voltage with temperature and includes at least one band-gap generator for supplying a power stage through an error amplifier and a comparator. The error amplifier is also supplied a regulated voltage which may be produced by the regulator itself. The at least one band-gap generator includes a plurality of band-gap generators being supplied by the regulated voltage and input a fraction of the regulated voltage through a voltage divider. The respective outputs of the band-gap generators are connected to a logic network which has an output connected to the power stage. The error amplifier and comparator may be included within each respective band-gap generator.

Abstract: A process and an integrated circuit are intended for obtaining an adjustable electrical resistance, in which a first voltage is applied to an integrated MOS transistor on its source, its gate and its substrate, and a second voltage is applied on its drain, the first and second voltages being able to initiate a breakdown of the MOS transistor by: avalanche of the drain/substrate junction; biasing of the parasitic bipolar transistor of the MOS transistor; irreversible breakdown of the drain/substrate junction; and shorting between the drain and the source.

Abstract: An input stage of an integrated circuit comprising a first and a second voltage divider, and a comparator, each voltage divider comprising a respective first MOS transistor in series with a diode-connected second MOS transistor connected between a first and a second supply rail, outputs of each divider being input to a comparator, the gate of the first MOS transistor of the first divider providing the circuit input and the gate of the first MOS transistor of the second divider being responsive to a reference voltage, where the aspect ratios of the first and second MOS transistors of the first divider are selected to overcome oxide stress when the circuit input voltage lies outside the voltages on the first and second supply rails.

Abstract: The present invention relates to a method of manufacturing the base and emitter regions of a bipolar transistor, including the steps of depositing a first heavily-doped P-type polysilicon layer; eliminating the first polysilicon layer in its central portion; growing a thermal oxide layer; performing a P-type implantation at a first dose; forming silicon nitride spacers at the internal periphery of the first layer; performing a second P-type implantation at a second dose; eliminating the central oxide layer; depositing a second N-type polysilicon layer; and performing a fast thermal anneal; the second dose being selected to optimize the characteristics of the base-emitter junction and the first dose being smaller than the second dose.

Abstract: An improved method of making semiconductor memory structures that include a memory matrix having non-volatile memory cells, each with a floating gate transistor and a selection transistor, each transistor provided with a gate electrode. Associated with the memory matrix is control circuitry, which also have control gates. The method includes forming the gate electrodes on top of the semiconductor substrate and then depositing a dielectric layer over the whole memory structure. A screening layer is deposited over the whole surface of the memory structure, and then part of it is removed, exposing a portion of the control circuitry. A portion of the dielectric layer is etched away in the non-covered portion of the control circuitry to form spacer regions, and the non-covered portion of the control circuitry is then implanted with a dopant.

Abstract: A process of forming on a monocrystalline-silicon body an etching-aid region of polycrystalline silicon; forming, on the etching-aid region a nucleus region of polycrystalline silicon surrounded by a protective structure having an opening extending as far as the etching-aid region; TMAH-etching the etching-aid region and the monocrystalline body to form a tub-shaped cavity; removing the top layer of the protective structure; and growing an epitaxial layer on the monocrystalline body and the nucleus region. The epitaxial layer, of monocrystalline type on the monocrystalline body and of polycrystalline type on the nucleus region, closes upwardly the etching opening, and the cavity is thus completely embedded in the resulting wafer.

Abstract: A configurable electronic circuit having configuration nodes is provided. Each of the configuration nodes is coupled to corresponding first circuitry that is non-modifiable during configuration and second circuitry that is modifiable during the configuration. The non-modifiable first circuitry selectively imposes one of at least a first potential and a second potential on the configuration node prior to configuration, and the modifiable second circuitry allows modification of the potential imposed on the configuration node by the non-modifiable first circuitry. In a preferred embodiment, the modifiable second circuitry includes at least one fuse that is in an intact state before configuration and that can be changed to a destroyed state after configuration. This enables a reduction in the number of fuses that have to be destroyed during the configuration of the circuit. Also provided is an information processing system that includes at least one configurable electronic circuit having configuration nodes.

Abstract: Electronic circuit comprising a first and a second current mirrors, an upstream active element arranged between an input of the first current mirror and an input of the second current mirror, each current mirror being provided with an output. The circuit comprises a first current source arranged in parallel with the input of the first current mirror and a second current source arranged in parallel with the input of the second current mirror, so that the current delivered to the active element is equal to the output current of each current mirror and that the input current of each current mirror is less than the current delivered to the active element by the input of each current mirror and by the associated current source.

Abstract: A power-on-reset circuit for delivering a power-on-reset pulse when a supply voltage ramps up from zero to a predetermined voltage includes a pull-down circuit portion for connecting an output node of the power-on-reset circuit to ground when the supply voltage reaches a predetermined upper threshold voltage and a pull-up circuit portion for connecting the output node to the supply voltage when the supply voltage reaches a predetermined upper threshold voltage. The pull-up circuit portion includes a transistor whose gate is polarized by a reference voltage taken at the terminals of a precision resistance traversed by a current delivered by a current generator, where the current is preferably a band-gap current proportional to the temperature of the circuit. The power-on-reset circuit is particularly suitable for microprocessors.

Abstract: A computer system comprising a microprocessor on a single integrated circuit chip having an on-chip CPU which includes: a data processing unit for executing instructions; a data link connected between a memory and the data processing unit for passing instructions to the data processing unit; a watch register for storing an instruction comparison code; and a watch comparator coupled to the data link for comparing the instructions passed on the data link with the instruction comparison code and generating a comparison output signal in dependence on the result of the comparison.

Abstract: A method for manufacturing a smart card in which a through-passage is produced in a central sheet. At least one face of the central sheet is provided with at least one metal coil having connection parts, and an electronic chip having electrical connection pads is inserted into the passage. At least some of the electrical connection pads of the chip are soldered to the connection parts of the coil, and the faces of the central sheet are provided with external covering sheets to form a stack of sheets. In a preferred method, the stack of sheets is hot pressed or laminated such that the material of the sheets is flowed and fills the space around the chip. A smart card is also provided. The smart card includes at least one metal coil having at least two connection parts, an electronic chip connected to the connection parts of the coil, a central sheet having a through-passage, and external covering sheets that grip the central sheet. The electronic chip is placed in the passage in the central sheet.

Abstract: A circuit for checking the parity of the contents of a register is provided. The register has a test mode in which a scan input of each flip-flop in the register is connected to a scan output of a preceding flip-flop to form a scan path. The parity checking circuit includes an XOR gate for at least each flip-flop from the second flip-flop to the last flip-flop of the register. Each XOR gate has one input connected to the normal output of the associated flip-flop, another input connected to the scan input for the flip-flop, and an output connected to the scan output of the flip-flop when not in the test mode. The result of the parity checking operation is generated at the output of the XOR gate associated with the last flip-flop of the register. In preferred embodiments, for each flip-flop of the register, the normal output of the flip-flop is supplied to the scan output in the test mode, and the output of the associated XOR gate is supplied to the scan output when not in the test mode.

Abstract: The present invention relates to a method for determining a characteristic of a periodic digital signal, including the steps of: defining a measurement period such that the ratio between the measurement period and the period of the digital signal is a ratio of integers; selecting a set of measurement periods in which the digital signal has substantially the same phase; defining a measurement time having a same position in each measurement period of the set; storing the value of the digital signal at each measurement time; shifting the measurement time by a predetermined pitch lower than one measurement period; repeating the two preceding steps until the measurement time of each measurement period has scanned a predetermined portion of the measurement period; and analyzing the succession of the noted values.

Abstract: The power supply device comprises a DC-DC converter circuit including a power switch and a driving stage. The driving stage has a compensation terminal on which a compensation voltage is present and which receives a biasing current, said driving stage comprising a control circuit having an output terminal connected to a control terminal of the power switch and disconnection-detecting means connected to said compensation terminal and generating a signal for permanent turning-off of said power switch when the biasing current drops below a current-threshold value. The driving stage moreover comprises over-voltage detecting means connected to the compensation terminal and generating a signal for temporary turning-off of said power switch when said compensation voltage exceeds a voltage-threshold value.

Abstract: A micro-pipeline type asynchronous circuit and a method for detecting and correcting soft error. The asynchronous circuit records in a first recording unit a signal output by a calculation unit and then records in a second recording unit the same signal delayed by at least the duration of the pulse of a soft error. The recorded signals then are compared in a comparer circuit. If they are identical, no soft error has been detected and the output signal is recorded after another delay that is longer than the pulse duration of the soft error, and a request signal is transmitted to a control unit of a next logic stage with a delay twice as long as the pulse duration of a soft error.

Abstract: A high-voltage bidirectional switch, including a high-voltage bidirectional switching element, and circuitry for making the switching element bistable and controllable by, at most, two low-voltage pulse signals.

Abstract: An apparatus and method for producing a wrap-around interconnect substrate (60) comprising a substrate (42) having semi-circular vias (62) having openings (64) created by separating through cylindrical vias (62) that were positioned along cutting lines (46a, 46b) that formed part of an integrated circuit substrate strip (40) prior to separation, is disclosed.

Abstract: A method and a related circuit structure are described for improving the effectiveness of ESD protection in circuit structures realized in a semiconductor substrate overlaid with an epitaxial layer and including at least one ESD protection lateral bipolar transistor realized in the surface of the epitaxial layer. The method consists of forming under the transistor an isolating well that isolates the transistor from the substrate. Advantageously, the transistor can be fully isolated from the substrate by first and second N wells which extend from the surface of the epitaxial layer down to and in contact with the buried well.

Abstract: A method of manufacturing a capacitor includes the steps of depositing a first metal level and etching it to leave in place a region corresponding to a first plate of a capacitor and an area of contact with an upper level; depositing an insulating layer; forming a first opening above the first capacitor plate; depositing a thin insulating layer; forming a second opening above the contact area; depositing a second metal level; removing by physico-chemical etching the second metal layer outside regions where it fills up the openings; and depositing a third metal level and leaving in place portions thereof.