Abstract: A self-disabling and self-recovering converter includes a transformer connected to a power source and has an auxiliary winding for providing a self-supply voltage after start-up, and an integrated circuit having circuitry and a plurality of pins connected thereto. The converter also includes at least one external line and a sensor connected thereto for an electrical or physical quantity to be monitored. The at least one external line is biased through a first pin with the self-supply voltage, and is functionally coupled to a second pin when a threshold is surpassed. A sectionable voltage clamp chain is connected between the auxiliary winding and a voltage reference. A self-recovery circuit having a first input is connected to the auxiliary winding and a second input is connected through the second pin to the at least one external line.

Abstract: A flip-flop circuit comprises a pair of cross-coupled inverters, each of which has a respective FET connected in series between it and the reference terminal, each inverter driving a transistor of an output inverter.

Abstract: A method is provided for defining programmed values of the boost and cut-off frequency parameters of a low pass filter of pre-equalization, of a read channel for a magnetic medium mass memory device, to ensure optimal functioning conditions of the adaptive filter of final equalization. The method includes pre-programming instantaneous digital values of the boost and cut-off frequency parameters of the low pass filter of pre-equalization for each magnetic medium, as a function of purposely sensed instantaneous operating parameters of the adaptive filter that carries out the definitive equalization of the signal during a trim scanning of the magnetic medium.

Abstract: A circuit and method are disclosed for determining whether a brushless polyphase motor is spinning in a reverse direction relative to spin direction during normal operation. The circuit receives a back emf signal of a first phase line and determines a polarity of the back emf signal following a back emf signal associated with a second phase line crossing a zero reference level. Based upon the determined polarity of the back emf signal of the first phase line, the circuit selectively asserts an output signal indicating that the motor is spinning in the reverse direction.

Abstract: A DC-DC converter having a current error amplifier and a voltage error amplifier connected in parallel to control the charging of the battery and a gradual turning off circuit for turning off gradually the current error amplifier in a battery charging end phase. In this way, the DC-DC converter is able to supply to the battery a battery charging current that remains constant until the battery full charge voltage is reached.

Abstract: An Ethernet device and the method for applying back pressure within an Ethernet communication network comprising the steps of asserting a back pressure pin of a media access control unit associated with a network communications port of an Ethernet device. In response to asserting the back pressure pin, only the back pressure continuous preamble of a packet is transmitted without a start-of-frame delimiter onto the network.

Abstract: A method is for compressing a digital image including a matrix of elements, with each element including at least one component of a different type for representing a pixel. The method includes splitting the digital image into a plurality of blocks, and calculating for each block a group of discrete cosine transform (DCT) coefficients for the components of each type, and quantizing the DCT coefficients of each group using a corresponding quantization table scaled by a gain factor for achieving a target compression factor. The method also includes further quantizing the DCT coefficients of each group using the corresponding quantization table scaled by a pre-set factor, and arranging the further quantized DCT coefficients in a zig-zig vector.

Abstract: A method of forming, on a single-crystal semiconductor substrate of a first material, quantum dots of a second material, including growing by vapor phase epitaxy the second material on the first material in optimal conditions adapted to ensuring a growth at a maximum controllable rate. In an initial step, a puff of a gas containing the second material is sent on the substrate, in conditions corresponding to a deposition rate much faster than the maximum controllable rate.

Abstract: Semiconductor device for high voltages including at least one power component and at least one edge termination. The edge termination includes a voltage divider including a plurality of MOS transistors in series, and the edge termination is connected between non-driveble terminals of said power component.

Abstract: A method is provided for carrying out a trimming operation on an integrated circuit having a trimming circuit portion which includes memory elements and a modification circuit for modifying the state of the memory elements, at least a first input or supply pin, an output pin, and a second supply pin. According to the method, a single pin is enabled to receive trimming data by biasing the pin to outside its operating range. A clock signal is obtained from a division of the bias potential of the pin, and the logic value of the trimming data is obtained from a different division of the bias potential of the pin. Serial acquisition of the data is enabled in accordance with the clock signal, and the data is transferred to the modification circuit.

Abstract: A wordline driver has enable circuitry optimized for positive-going input transitions and disable circuitry optimized for transitions in a disable input which would cause the output to become disabled. The optimization is achieved by suitably dimensioning the transistors in the respective enable and disable circuits for suitable current-carrying ability.

Abstract: A phase-calculation circuit includes a buffer, an approximation circuit, and an interpolator. The buffer receives and stores first and second samples of a periodic signal having a peak amplitude. The approximation circuit linearly approximates a portion of the periodic signal, and calculates the relative phase of one of the samples within the signal portion. The interpolator then calculates the absolute phase of the one sample with respect to a predetermined point of the signal using the relative phase of the sample within the signal portion and the values of the first and second samples. Such a circuit can be used to decrease the alignment-acquisition time of a digital timing-recovery loop, and thus allows a shortening of the preamble and a corresponding increase in the data-storage density of a disk. In one application, the circuit determines an initial phase difference between a disk-drive read signal and a read-signal sample clock.

Abstract: A test structure includes a single current-measuring means for measuring current between a supply terminal and ground, and first and second branches for measuring capacitance between first and second metal lines. The first branch includes a first switch coupled between the current-measuring means and the first line, and a second switch coupled between the first line and ground. Similarly, the second branch includes a third switch coupled between the current-measuring means and the second line, and a fourth switch coupled between the second line and ground. A method for testing a circuit is also provided.

Abstract: A digital signal output circuit is provided. The digital signal output circuit includes capacitor forming means connected as an integrator, charging means, discharging means, means for selectively coupling, and a digital signal output. The charging means selectively charges the capacitor forming means with a constant charging current, and the discharging means selectively discharges the capacitor forming means with a constant discharging current. The means for selectively coupling selectively couples the capacitor forming means to the charging means and to the discharging means as a function of data to be transmitted by the digital signal. Additionally, the digital signal output is coupled to the capacitor forming means so as to establish a rising edge of the digital signal when the capacitor forming means is coupled to the charging means and a falling edge of the digital signal when the capacitor forming means is coupled to the discharging means.

Abstract: Circuitry for reading from and writing to memory cells of a group of memory cells. The circuitry comprises read circuitry and write circuitry each connectable to bit lines associated with respective ones of the memory cells. The read circuitry is arranged to read from the cells and the write circuitry is arranged to write to the cells. Wherein the read circuitry and write circuitry are configured so that more cells in the group can be simultaneously written to during a write operation than can be simultaneously read from during a read operation.

Abstract: An address binary counter for an interleaved having an array of memory cells being divided into a first bank of memory cells and a second bank of memory cells includes as many stages as the bits that may be stored in the memory cells of a row of one of the banks, and a carry calculation network. The interleaved memory operates in a burst access mode enabled by an enabling signal. The carry calculation network includes an ordered group of independent carry generators. Each independent carry generator includes a certain number of stages, with each stage having inputs receiving its own enabling bit and a number of consecutive bits of a row of the bank equal to the number of stages, orderly starting from the least significant bit. The enabling bit of the first carry generator of the ordered group is the enabling signal, and the enabling bit of any other carry generator of the ordered group is the logic AND of the enabling signal and of the input bits of the preceding carry generator of the ordered group.

Abstract: An IC isolation structure includes a recess disposed in a conductive layer having a surface portion. The recess has a side wall adjacent to the surface portion, and the isolation structure also includes an insulator disposed in the recess and overlapping the surface portion. Thus, if a transistor is disposed in the conductive layer adjacent to the recess side wall, the overlapping portion of the insulator increases the distance between the upper recess corner and the gate electrode. This increased distance reduces hump effects to tolerable levels.

Abstract: Semiconductor power device including a semiconductor layer of a first type of conductivity, wherein a body region of a second type of conductivity including source regions of the first type of conductivity is formed, a gate oxide layer superimposed to the semiconductor layer with an opening over the body region, polysilicon regions superimposed to the gate oxide layer, and regions of a first insulating material superimposed to the polysilicon regions. The device includes regions of a second insulating material situated on a side of both the polysilicon regions and the regions of a first insulating material and over zones of the gate oxide layer situated near the opening on the body region, oxide regions interposed between the polysilicon regions and the regions of a second insulating material, oxide spacers superimposed to the regions of a second insulating material.

Abstract: A control device is provided for controlling a selector switch of a high voltage input having at least one cascode stage with MOS transistors. The control device includes a reference voltage generation circuit and a control circuit. The reference voltage generation circuit generates reference voltages from the high voltage input and provides one or more output voltages for the biasing of the MOS transistors of the cascode stage. The control circuit controls the reference generation circuit on the basis of a binary control signal, so as to either set the bias voltages at the level of the logic supply voltages to enable the switching of the selector switch even at low values of the high voltage input, or to enable the bias voltages to be set by the reference generation circuit.

Abstract: A contact opening to a silicon substrate within which a metal contact is to be formed is cleaned by soft sputter etch to clean the substrate surface and remove any residue which would interfere with formation of a continuous silicide layer across the contact region. Contact profile protrusion at the interface between two dielectrics forming the insulating material through which the contact opening is formed is also reduced by the soft sputter etch. A barrier is formed over the contact region utilizing two discrete deposition steps, preferably separated by an interval of time and employing different process parameters, to provide a shift in the grain boundaries between the two barrier layers, creating diffusion traps at grain discontinuities inhibiting the diffusion of metal through the barrier layer. Performance of the barrier layer in preventing junction spiking is thereby increased.