Abstract: Solid state image sensors, and methods of operation thereof, includes an array of photosensitive pixels arranged in rows and columns and in which pixel data signals are read out from the pixels via column circuits, which introduces column fixed pattern noise to the signals. The signals are selectively inverted at the inputs to the column circuits and the inversion is reversed following output from the column circuits. Each column circuit may include an analog-to-digital converter and a digital inverter for inverting digital output therefrom. The selective inversion may be applied to alternate rows or groups of rows of the pixel data, and may be applied differently to different frames of the pixel data. These techniques result in column fixed pattern noise being modulated in a manner which makes the noise less apparent to the eye, and which facilitates subsequent cancellation of the noise.

Abstract: At least a first base signal and a second base signal are mutually in quadrature and both are capable of mutually exhibiting a quadrature error. These signals are used to formulate two pairs of delayed signals that includes a first delayed signal that is delayed with respect to the first base signal, a second signal delayed in phase opposition with respect to the first delayed signal, a third signal delayed with respect to the second base signal, and a fourth delayed signal in phase opposition with respect to the third delayed signal. The value of each of the delays is continuously adjusted using two differential signals arising from a direct or an indirect cross-mixing of the two pairs of delayed signals to obtain the four delayed signals virtually in quadrature.

Abstract: The invention relates to a circuit generating a voltage signal which is independent of temperature and has low sensitivity to variations in process parameters, comprising at least an output MOS transistor through which an output current flows, it being connected to a first voltage reference and having a gate terminal connected to a bias network, in turn connected between a second voltage reference and the first voltage reference. The circuit of this invention includes a bias network comprising at least first and second MOS transistors connected in a diode configuration, connected in series between said first and second voltage references, and connected to the second voltage reference through a current generator element having a thermal gradient that approximates the thermal gradient of a MOS transistor.

Abstract: A cellular telephone includes a plurality of power amplifiers having a common operating region. If one of the amplifiers has to be deselected, a desired moment for the switching to another amplifier is defined based upon a predetermined transmission interrupt criterion. The power continues to be adjusted with the currently selected amplifier until the instant of switch over. Switching to the other amplifier may then be performed after the transmission has been interrupted.

Abstract: A portable system carried by a user for assessing movement of the user includes at least one motion sensor adjacent a portion of the user's body under observation. An analog-to-digital converter is connected to the motion sensor for converting an analog signal therefrom into a digital signal. A logic circuit is connected to the analog-to-digital converter for calculating parameters based upon the digital signal. A first fuzzy logic processing circuit is connected to the logic circuit for processing the calculated parameters and for generating corresponding fuzzy classification labels based upon movement of the portion of the user's body under observation during an interval of time. A memory is connected to the first fuzzy logic processing circuit for storing at least one of the calculated parameters and the fuzzy classification labels.

Abstract: A non-volatile memory cell includes a MOS transistor having a ring arrangement and comprising a floating gate, a center electrode at a center of the ring arrangement and surrounding the floating gate, and at least one peripheral electrode along a periphery of the ring arrangement.

Abstract: A method for testing a programmable, nonvolatile memory including a matrix of memory cells is provided. A plurality of memory cells are programmed. The programmed memory cells are addressed in succession to identify a lowest of threshold voltage levels. The addressing for each memory location includes applying a selection voltage that is lower than the lowest threshold voltage level corresponding to a memory location currently being addressed. The bits are read from the programmed memory cells for the memory location currently being addressed. The reading is repeated while progressively changing the selection voltage supplied to the word line corresponding to the memory location currently being addressed until it is detected that at least one of the bits of the memory location currently being addressed has switched from a first logic level corresponding to a reading of a programmed memory cell to a second logic level corresponding to a reading of a non-programmed memory cell.

Abstract: The present invention refers to a digital to analog conversion circuit able to transform an input digital signal having n bit in a signal having a thermometric code and to convert it in an analog output signal.

Abstract: An integrated circuit provides for a connection port having a serial data input pin and a serial data output pin, on-chip functional circuitry and test logic, and a test access port controller connected to effect communication of serial data across the chip boundary via said input and output pins. The test access port controller is connectable to the test logic in a first mode of operation to effect communication of serial test data under control of an incoming clock signal and is operable in a second mode of operation to communication data as a sequence of serial bits according to a predetermined protocol between the connection port and the on-chip functional circuitry. The integrated circuit includes an error detection circuit for detecting an error condition in the protocol and gating circuitry responsive to detection of the error condition to prevent communication of subsequent data until the error condition is detected as having been removed.

Abstract: A method for controlled soft programming of a plurality of non-volatile memory cells, having bulk terminals connected to one another and to a common bulk line. The method includes supplying at least one soft programming pulse to the plurality of memory cells for a time interval. In this step, a bulk voltage with a rising negative ramp is applied to the common bulk line for the time interval. By this means, the threshold voltage of the cells is increased by body effect, and initially only the most depleted cells are soft programmed, with a limited drain current. Subsequently, when the bulk voltage increases, the cells with a higher threshold voltage are also soft programmed, until all the cells have reached the required minimum threshold value.

Abstract: A redundant electric fuse circuit is provided that includes a plurality of fuses coupled in series and each having a fuse control device operable for generating a current through each fuse sufficient to blow the fuse. A first fuse control signal is activated to generate a sufficient current through one of the fuses to blow the fuse. A second fuse control signal is activated to generate a sufficient current through the other fuse to blow that fuse. The electric fuse circuit provides redundancy thereby increasing the yield of integrated circuits by reducing the probability that a defective fuse (i.e., a fuse that reforms after blowing) will cause a fatal defect in the integrated circuit.

Abstract: A radiation hardened memory device having static random access memory cells includes active gate isolation structures to prevent leakage currents between active regions formed adjacent to each other on a substrate. The active gate isolation structure includes a gate oxide and polycrystalline silicon gate layer electrically coupled to a voltage terminal resulting in an active gate isolation structure that prevents a conductive channel extending from adjacent active regions from forming. The gate oxide of the active gate isolation structures is relatively thin compared to the conventional oxide isolation regions and thus, will be less susceptible to any adverse influence from trapped charges caused by radiation exposure.

Abstract: A serial-flash, EPROM, EEPROM, or flash EEPROM nonvolatile memory in AMG configuration includes a byte enable transistor having an input terminal, connected to a control gate line and receives an input voltage, an output terminal, connected to at least one memory cell and supplying an output voltage, a control terminal connected to a word line, and a bulk region housing conductive regions connected to the input and output terminals. The byte enable transistor is a P-channel MOS transistor, the bulk region whereof is biased to a bulk voltage that is not lower than the input voltage.

Abstract: A manufacturing process including: forming a substrate and insulating layer including a tunnel area; and simultaneously forming a floating gate region of a memory transistor and a lower gate portion of a selection transistor, the floating gate region internally forming a hole, one side of which delimits, together with an external side of the floating gate region, a portion of tunnel arranged above the tunnel area; a dielectric material layer is then deposited, and fills the hole of the floating gate region; the structure is planarized by CMP, and an insulating region of dielectric material is formed; and a control gate region is formed above the floating gate region and simultaneously an upper gate portion is formed above the lower gate portion. The upper and lower gate portions form a control gate region of the selection transistor. In this way, the upper gate portion and the control gate region are substantially on the same level.

Abstract: A method and device reduces consumption of a microcontroller, allowing the microcontroller to enter into an “active halt” mode in which the central processing unit, the internal peripheral circuits, and a clock tree are deactivated. The main oscillator is operative and delivers an oscillating signal. An internal interruption returns the microcontroller back into the run mode and is generated after a time delay obtained by an internal circuit activated by the oscillating signal.

Abstract: A monolithic bidirectional switch formed in a semiconductor substrate of a first conductivity type having a front surface and a rear surface, including a first main vertical thyristor, the rear surface layer of which is of the second conductivity type, a second main vertical thyristor, the rear surface layer of which is of the first conductivity type. A structure for triggering each of the first and second main thyristors is arranged to face regions mutually distant from the two main thyristors, the neighboring portions of which correspond to a region for which, for the first main thyristor, a short-circuit area between cathode and cathode gate is formed.

Abstract: A semiconductor memory cell that includes a word line, two bit lines, a precharge line, and two cross-coupled inverters. Each of the inverters is formed by a P-channel transistor and an N-channel transistor. Additionally, a first access transistor selectively couples one bit line to the output of one inverter, and a second access transistor selectively couples the other bit line to the output of the other inverter. One terminal of the N-channel transistor of each of the inverters is connected to the precharge line. In a preferred embodiment, the access transistors are P-channel transistors and the gate terminal of each PMOS access transistor is connected to the word line. Additionally, the present invention provides a method of writing data to a semiconductor memory cell that is connected to a pair of bit lines.

Abstract: Self-aligned etching process for providing a plurality of mutually parallel word lines in a first conducting layer deposited over a plagiarized architecture obtained starting from a semiconductor substrate on which is provided a plurality of active elements extending along separate parallel lines e.g., memory cell bit lines and comprising gate regions made up of a first conducting layer, an intermediate dielectric layer and a second conducting layer with said regions being insulated from each other by insulation regions to form said architecture with said word lines being defined photolithographically by protective strips implemented by means of: a vertical profile etching for complete removal from the unprotected areas of the first conducting layer of the second conducting layer and of the intermediate dielectric layer respectively, and a following isotropic etching of the first conducting layer.

Abstract: A voltage/current controller device, particularly for interleaving switching regulators, comprises: a DC/DC converter having a plurality of modules, with each module including a drive transistor pair connected in series between first and second supply voltage references, a current sensor connected to one transistor in the pair, and a current read circuit connected to the sensor. Advantageously, the read circuit comprises a transconductance amplifier connected across the current sensor to sense a voltage signal related to a load current being applied to each module, the transconductance amplifier reading the voltage signal with the transistor in the conducting state.

Abstract: A first-in, first-out (FIFO) memory cell architecture is provided in which one node of the latch in the FIFO memory cell is connected to the gate of the pass transistor. Further, the bit line is connected to the source of the pass transistor, and the word line is connected to the drain of the pass transistor to provide a stable memory cell requiring less area for implementation.